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HCPL-7720-060

产品描述Logic IC Output Optocoupler, 1-Element, 3750V Isolation, 0.300 INCH, DIP-8
产品类别光电   
文件大小438KB,共18页
制造商HP(Keysight)
官网地址http://www.semiconductor.agilent.com/
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HCPL-7720-060概述

Logic IC Output Optocoupler, 1-Element, 3750V Isolation, 0.300 INCH, DIP-8

HCPL-7720-060规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称HP(Keysight)
包装说明0.300 INCH, DIP-8
Reach Compliance Codeunknown
Is SamacsysN
其他特性UL RECOGNIZED, VDE APPROVED
配置SINGLE
最大正向电流0.00001 A
最大绝缘电压3750 V
JESD-609代码e0
安装特点THROUGH HOLE MOUNT
元件数量1
最大通态电流0.01 A
最高工作温度85 °C
最低工作温度-40 °C
光电设备类型LOGIC IC OUTPUT OPTOCOUPLER
最大功率耗散0.295 W
最小供电电压4.5 V
表面贴装NO
端子面层Tin/Lead (Sn/Pb)
Base Number Matches1

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Agilent
HCPL-0720/7720 and HCPL-0721/7721
40 ns Propagation Delay,
CMOS Optocoupler
Data Sheet
Features
• +5 V CMOS compatibility
• 20 ns maximum prop. delay skew
Description
Available in either an 8-pin DIP or
SO-8 package style respectively, the
HCPL-772X or HCPL-072X
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with very
low power consumption. The
HCPL-772X/072X require only two
bypass capacitors for complete
CMOS compatability.
Basic building blocks of the
HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED
and a CMOS detector IC. A CMOS
logic input signal controls the
LED driver IC which supplies
current to the LED. The detector
IC incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
• High speed: 25 MBd
• 40 ns max. prop. delay
• 10 kV/µs minimum common mode
rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals
UL recognized
3750 V rms for 1 min. per
UL 1577
CSA component acceptance
notice #5
IEC/EN/DIN EN 60747-5-2
– V
IORM
= 630 Vpeak for
HCPL-772X option 060
– V
IORM
= 560 Vpeak for
HCPL-072X option 060
Applications
• Digital fieldbus isolation: CC-Link,
DeviceNet, Profibus, SDS
• AC plasma display panel level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
Functional Diagram
TRUTH TABLE
(POSITIVE LOGIC)
V
I
, INPUT
V
I
2
I
O
*
3
LED1
GND
1
4
SHIELD
5
GND
2
6
V
O
7
NC*
H
L
LED1
OFF
ON
V
O
, OUTPUT
H
L
**V
DD1
1
8
V
DD2
**
* Pin 3 is the anode of the internal LED and must be left unconnected for
guaranteed data sheet performance. Pin 7 is not connected internally.
**A 0.1
µF
bypass capacitor must be connected between pins 1 and 4, and
5 and 8.
CAUTION:
It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.

 
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