CAT1163
Supervisory Circuits with
I
2
C Serial CMOS EEPROM,
Precision Reset Controller
and Watchdog Timer (16K)
Description
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The CAT1163 is a complete memory and supervisory solution for
microcontroller−based systems. A serial EEPROM memory (16K)
with hardware memory write protection, a system power supervisor
with brown out protection and a watchdog timer are integrated
together in low power CMOS technology. Memory interface is via an
I
2
C bus.
The 1.6−second watchdog circuit returns a system to a known good
state if a software or hardware glitch halts or “hangs” the system. The
CAT1163 watchdog monitors the WDI input pin.
The power supply monitor and reset circuit protects memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, a reset pin can be used as a
debounced input for pushbutton manual reset capability.
The CAT1163 memory features a 16−byte page. In addition,
hardware data protection is provided by a write protect pin WP and by
a V
CC
sense circuit that prevents writes to memory whenever V
CC
falls
below the reset threshold or until V
CC
reaches the reset threshold
during power up.
Available packages include an 8−pin DIP and a surface mount,
8−pin SO package.
Features
PDIP−8
CASE 646AA
SOIC−8
CASE 751BD
PIN CONFIGURATION
PDIP 8 Lead
SOIC 8 Lead
WDI
RESET
WP
GND
1
2
3
4
CAT1163
8
7
6
5
V
CC
RESET
SCL
SDA
PIN FUNCTIONS
Pin Name
WDI
RESET
WP
GND
SDA
SCL
RESET
V
CC
Function
Watchdog Timer Input
Active Low Reset I/O
Write Protect
Ground
Serial Data/Address
Clock Input
Active High Reset I/O
Power Supply
•
•
•
•
•
•
Watchdog Timer Input (WDI)
400 kHz I
2
C Bus Compatible
2.7 V to 6.0 V Operation
Low Power CMOS Technology
16−Byte Page Write Buffer
Built−in Inadvertent Write Protection
♦
V
CC
Lock Out
♦
Write Protection Pin, WP
•
Active High or Low Reset
♦
Precision Power Supply Voltage Monitor
♦
5 V, 3.3 V and 3 V Systems
♦
Five Threshold Voltage Options
•
1,000,000 Program/Erase Cycles
•
Manual Reset
ORDERING INFORMATION
For Ordering Information details, see page 10.
•
•
•
•
100 Year Data Retention
8−Pin DIP or 8−Pin SOIC
Commercial and Industrial Temperature Ranges
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 10
1
Publication Order Number:
CAT1163/D
CAT1163
Table 1. RESET THRESHOLD OPTION
Part Dash
Number
−45
−42
−30
−28
−25
Minimum
Threshold
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
D OUT
ACK
V CC
GND
WORDADDRESS
BUFFERS
COLUMN
DECODERS
SENSEAMPS
SHIFT REGISTERS
SDA
START/STOP
LOGIC
16K
EEPROM
XDEC
WP
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
WATCHDOG
Precision
Vcc Monitor
WDI
RESET RESET
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CAT1163
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
−2.0
to V
CC
+ 2.0
−2.0
to 7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Note 3)
T
DR
(Note 3)
V
ZAP
(Note 3)
I
LTH
(Notes 3 & 4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
Table 4. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 6.0 V, unless otherwise specified.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current
Test Conditions
f
SCL
= 100 kHz
V
CC
= 3.3 V
V
CC
= 5 V
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (SDA)
I
OL
= 3 mA, V
CC
= 3.0 V
V
IN
= GND or V
CC
V
IN
= GND or V
CC
−1
V
CC
x 0.7
Min
Typ
Max
3
40
50
2
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
V
V
V
Table 5. CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
I/O
(Note 3)
C
IN
(Note 3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
Test Conditions
V
I/O
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
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CAT1163
Table 6. AC CHARACTERISTICS
V
CC
= 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF.
V
CC
= 2.7 V
−
6 V
Symbol
F
SCL
T
1
(Note 1)
t
AA
t
BUF
(Note 1)
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
R
(Note 1)
t
F
(Note 1)
t
SU; STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
50
1
300
0.6
100
Parameter
Min
Max
100
200
3.5
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
V
CC
= 4.5 V
−
5.5 V
Min
Max
400
200
1
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. POWER−UP TIMING
(Notes 1 and 2)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Min
Typ
Max
1
1
Units
ms
ms
2. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specific operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol
t
WR
Write Cycle Time
Parameter
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 9. RESET CIRCUIT CHARACTERISTICS
Symbol
t
GLITCH
V
RT
V
OLRS
V
OHRS
V
TH
Glitch Reject Pulse Width
Reset Threshold Hysteresis
Reset Output Low Voltage (I
OLRS
= 1 mA)
Reset Output High Voltage
Reset Threshold (V
CC
= 5 V), (CAT1163−45)
Reset Threshold (V
CC
= 5 V), (CAT1163−42)
Reset Threshold (V
CC
= 3.3 V), (CAT1163−30)
Reset Threshold (V
CC
= 3.3 V), (CAT1163−28)
Reset Threshold (V
CC
= 3 V), (CAT1163−25)
t
PURST
t
WP
t
RPD
V
RVALID
Power−Up Reset Timeout
Watchdog Period
V
TH
to RESET Output Delay
RESET Output Valid
1
V
CC
−
0.75
4.50
4.25
3.00
2.85
2.55
130
1.6
5
4.75
4.50
3.15
3.00
2.70
270
ms
s
ms
V
15
0.4
Parameter
Min
Typ
Max
100
Units
ns
mV
V
V
V
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CAT1163
PIN DESCRIPTION
WDI:
WATCHDOG INPUT
If there is no transition on the WDI for more than
1.6 seconds, the watchdog timer times out.
WP:
WRITE PROTECT
If the pin is tied to V
CC
the entire memory array becomes
Write Protected (READ only). When the pin is tied to GND
or left floating normal read/write operations are allowed to
the device.
RESET/RESET:
RESET I/O
These are open drain pins and can be used as reset trigger
inputs. By forcing a reset condition on the pins the device
will initiate and maintain a reset condition. The RESET pin
must be connected through a pulldown resistor, and the
RESET pin must be connected through a pull−up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL:
Serial Clock
Serial clock input.
DEVICE OPERATION
Reset Controller Description
The CAT1163 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
RESET outputs. During power−up, the RESET outputs
remain active until V
CC
reaches the V
TH
threshold and will
continue driving the outputs for approximately 200 ms
(t
PURST
) after reaching V
TH
. After the t
PURST
timeout
interval, the device will cease to drive the reset outputs. At
this point the reset outputs will be pulled up or down by their
respective pull up/down resistors. During power−down, the
RESET outputs will be active when V
CC
falls below V
TH
.
The RESET outputs will be valid so long as V
CC
is > 1.0 V
(V
RVALID
).
The RESET pins are I/Os; therefore, the CAT1163 can act
as a signal conditioning circuit for an externally applied
manual reset. The inputs are edge triggered; that is, the
t
GLITCH
RESET input in the CAT1163 will initiate a reset timeout
after detecting a low to high transition and the RESET input
in the CAT1163 will initiate a reset timeout after detecting
a high to low transition.
Watchdog Timer
The Watchdog Timer provides an independent protection
for microcontrollers. During a system failure, the CAT1163
will respond with a reset signal after a time−out interval of
1.6 seconds for a lack of activity. The CAT1163 is designed
with the Watchdog Timer feature on the WDI input. If the
microcontroller does not toggle the WDI input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on WDI.
As long as the reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
V
TH
V
RVALID
V
CC
t
PURST
t
RPD
t
PURST
RESET
t
RPD
RESET
Figure 1. RESET Output Timing
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