MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Product Preview
Low-Voltage 1:22 Differential
PECL/HSTL Clock Driver
The MC100EP223 is a low skew 1–to–22 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The selected signal is fanned out to 22 identical differential
outputs.
•
•
•
•
•
•
•
•
200ps Part–to–Part Skew
50ps Output–to–Output Skew
Differential Design
Open Emitter HSTL Compatible Outputs
3.3V V
CC
Both PECL and HSTL Inputs
75kΩ Input Pulldown Resistors
Thermally Enhanced 64 lead Exposed Pad LQFP
MC100EP223
See Upgrade Product – MC100ES6223
LOW–VOLTAGE
1:22 DIFFERENTIAL
PECL/HSTL CLOCK DRIVER
Freescale Semiconductor, Inc...
7
The EP223 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate–to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent t
pd
distributions
TC SUFFIX
from lot to lot. The net result is a dependable, guaranteed low skew
64–LEAD LQFP PACKAGE
device.
CASE 840K
The EP223 HSTL outputs are not realized in the conventional
manner. To minimize part–to–part and output–to–output skew, the HSTL
compatible output levels are generated with an open emitter
architecture. The outputs are pulled down with 50Ω to ground, rather
than the typical 50Ω to V
DDQ
pullup of a “standard” HSTL output.
Because the HSTL outputs are pulled to ground, the EP223 does not
utilize the V
DDQ
supply of the HSTL standard. The output levels are
derived from V
CC
.
In the case of an asynchronous control, there is a chance of
generating a ‘runt’ clock pulse when the device is enabled/disabled. To
avoid this, the output enable (OE) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into
50Ω, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In
the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will
mean a loss of skew margin.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Rev 2
656
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
VCCO
VCCO
Q10B
Q12B
Q13B
Q11B
Q7B
Q8B
Q9B
Q10
Q12
Q13
Q11
Q7
Q8
Q9
MC100EP223
48
VCCO
Q6B
Q6
Q5B
Q5
Q4B
Q4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCCO
Q14
Q14B
Q15
Q15B
Q16
Q16B
Q17
Q17B
Q18
Q18B
Q19
Q19B
Q20
Q20B
VCCO
Freescale Semiconductor, Inc...
Q3B
Q3
Q2B
Q2
Q1B
Q1
Q0B
Q0
VCCO
MC100EP223
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PECL_CLKB
HSTL_CLKB
PECL_CLK
VCCO
VCCI
HSTL_CLK
CLK_SEL
VCCO
GND
OE
NC
NC
NC
NC
Q21B
Q21
7
Figure 1. 64–Lead Pinout
(Top View)
CLK_SEL
PIN NAMES
Pins
HSTL_CLK, HSTL_CLKB
PECL_CLK, PECL_CLKB
Q0:21, Q0B:21B
CLK_SEL
OE
GND
VCCI
VCCO
Function
Differential HSTL Inputs
Differential PECL Inputs
Differential HSTL Outputs
Active Clock Select Input
Output Enable
Ground
Core VCC
I/O VCC
HSTL_CLK
HSTL_CLK
0
22
22
Q
Q0 - Q21
Q0 - Q21
LVPECL_CLK
LVPECL_CLK
OE
1
LEN
D
Figure 2. Logic Symbol
SIGNAL GROUPS
FUNCTION
OE
0
0
1
1
CLK_SEL
0
1
0
1
Q0:21, Q0B:21B
Q = Low, QB = High
Q = Low, QB = High
HSTL_CLK, HSTL_CLKB
PECL_CLK, PECL_CLKB
Level
HSTL
HSTL
LVPECL
LVCMOS/LVTTL
Direction
Input
Output
Input
Input
Signal
HSTL_CLK, HSTL_CLKB
Q0:21, Q0B:21B
PECL_CLK, PECL_CLKB
CLK_SEL, OE
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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657
MC100EP223
HSTL DC CHARACTERISTICS
Freescale Semiconductor, Inc.
0°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
X
Characteristic
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Crossover Voltage
V
X
+0.1
–0.3
0.68
Min
Typ
Max
Min
1.0
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
V
0.4
1.6
V
X
–0.1
0.9
V
V
V
V
PECL DC CHARACTERISTICS
0°C
Symbol
Characteristic
Input HIGH Voltage (Note 1.)
Input LOW Voltage (Note 1.)
Input HIGH Current
Min
2.135
1.490
Typ
Max
2.420
1.825
150
Min
2.135
1.490
25°C
Typ
Max
2.420
1.825
150
Min
2.135
1.490
85°C
Typ
Max
2.420
1.825
150
Unit
V
V
µA
Freescale Semiconductor, Inc...
V
IH
V
IL
I
IH
1. These values are for V
CC
= 3.3V. Level specifications vary 1:1 with V
CC
.
AC CHARACTERISTICS
(V
EE
= GND, V
CC
=V
CC(min)
to V
CC(max)
)
0°C
Symbol
t
PLH
,
t
PHL
t
skew
f
max
V
PP
V
CMR
t
r
, t
f
Characteristic
Propagation Delay to Output
IN (Differential)
Within–Device Skew
Part–to–Part Skew (Diff)
Maximum Input Frequency
Minimum Input Swing PECL_CLK
Common Mode Range PECL_CLK
Output Rise/Fall Time (20–80%)
300
600
300
600
300
600
600
Min
Typ
1.0
50
200
250
600
Max
Min
25°C
Typ
1.0
50
200
250
600
Max
Min
85°C
Typ
1.0
50
200
250
ps
MHz
mV
V
ps
Max
Unit
ns
7
Power Supply Characteristics
Symbol
V
CCI
V
CCO
Core V
CC
I/O V
CC
Characteristic
Min
3.0
1.6
Typ
3.3
1.8
Max
3.6
2.0
Unit
V
V
I
CC
I
EE
Power Supply Current
Power Supply Current
mA
mA
658
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100EP223
The MC100EP223 uses a thermally enhanced 64 lead
LQFP package. This package provides the low thermal imped-
ance that supports the power consumption of the
MC100EP223 high-speed bipolar integrated circuit and eases
the power management task for the system design. An ex-
posed pad at the bottom of the package establishes thermal
conductivity from the package to the printed circuit board. In
order to take advantage of the enhanced thermal capabilitites
of this package, it is recommended to solder the exposed pad
of the package to the printed circuit board. The attachment
process for exposed pad package is the same as for any stan-
dard surface mount package. Vias are recommended from the
pad on the board down to an appropriate plane in the board
that is capable of distributing the heat. In order to supply
enough solder paste to fill those vias and not starve the solder
joints, it may be required to stencil print solder paste onto the
printed circuit pad. This pad should match the dimensions of
the exposed pad. The dimensions of the exposed pad are
shown on the package outline in this specification. For thermal
system analysis and junction temperature calculation the ther-
mal resistance parameters of the package is provided:
Thermal Resistance
Convection
LFPM
Natural
100
200
400
800
a.
b.
c.
d.
R
THJAa
°C/W
57.1
50.0
46.9
43.4
38.6
R
THJAb
°C/W
24.9
21.3
20.0
18.7
16.9
MC100EP223
R
THJCc
°C/W
R
THJBd
°C/W
15.8
9.7
Freescale Semiconductor, Inc...
Junction to ambient, single layer test board, per JESD51-6
Junction to ambient, four conductor layer test board (2S2P), per
JES51-6
Junction to case, per MIL-SPEC 883E, method 1012.1
Junction to board, four conductor layer test board (2S2P) per
JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations to
their particular application. The exposed pad of the
MC100EP223 package does not have an electrical low imped-
ance path to the substrate of the integrated circuit and its termi-
nals.
7
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
659
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