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MC10102
Quad 2-Input NOR Gate
The MC10102 is a quad 2–input NOR gate. The MC10102 provides
one gate with OR/NOR outputs.
•
P
D
= 25 mW typ/gate (No Load)
•
t
pd
= 2.0 ns typ
•
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4
5
6
7
10
11
12
13
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
2
3
14
16
15
9
PDIP–16
P SUFFIX
CASE 648
1
1
PLCC–20
FN SUFFIX
CASE 775
10102
AWLYYWW
MC10102P
AWLYYWW
CDIP–16
L SUFFIX
CASE 620
1
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MARKING
DIAGRAMS
16
MC10102L
AWLYYWW
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
B
OUT
A
IN
A
IN
B
IN
B
IN
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
D
OUT
C
OUT
D
IN
D
IN
C
IN
C
IN
D
OUT
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC10102L
MC10102P
MC10102FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10102/D
MC10102
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
Test
8
12
12
9
9
15
15
9
9
15
15
9
9
15
15
9
9
15
15
0.5
–1.060
–1.060
–1.060
–1.060
–1.890
–1.890
–1.890
–1.890
–1.080
–1.080
–1.080
–1.080
–1.655
–1.655
–1.655
–1.655
–0.890
–0.890
–0.890
–0.890
–1.675
–1.675
–1.675
–1.675
–30°C
Min
Max
29
425
0.5
–0.960
–0.960
–0.960
–0.960
–1.850
–1.850
–1.850
–1.850
–0.980
–0.980
–0.980
–0.980
–1.630
–1.630
–1.630
–1.630
–0.810
–0.810
–0.810
–0.810
–1.650
–1.650
–1.650
–1.650
Min
+25°C
Typ
20
Max
26
265
0.3
–0.890
–0.890
–0.890
–0.890
–1.825
–1.825
–1.825
–1.825
–0.910
–0.910
–0.910
–0.910
–1.595
–1.595
–1.595
–1.595
–0.700
–0.700
–0.700
–0.700
–1.615
–1.615
–1.615
–1.615
Min
+85°C
Max
29
265
Unit
mAdc
µAdc
µAdc
Vdc
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
I
inH
I
inL
Output Voltage
Logic 1
V
OH
Output Voltage
Logic 0
V
OL
Vdc
Threshold Voltage
Logic 1
V
OHA
Vdc
Threshold Voltage
Logic 0
V
OLA
Vdc
Switching Times (50Ω Load)
Propagation Delay
t
12+15–
t
12–15+
t
12+9+
t
12–9–
t
15+
t
9+
t
15–
t
9–
15
15
9
9
15
9
15
9
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
3.1
3.1
3.1
3.1
3.6
3.6
3.6
3.6
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.9
2.9
2.9
2.9
3.3
3.3
3.3
3.3
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
3.3
3.3
3.3
3.3
3.7
3.7
3.7
3.7
ns
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
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2
MC10102
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
12
12
9
9
15
15
9
9
15
15
9
9
15
15
9
9
15
15
12
13
12
12
V
IHmax
–0.890
–0.810
–0.700
V
ILmin
–1.890
–1.850
–1.825
V
IHAmin
–1.205
–1.105
–1.035
V
ILAmax
–1.500
–1.475
–1.440
V
EE
–5.2
–5.2
–5.2
(V
CC
)
Gnd
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
+2.0 V
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
8
8
8
8
8
8
8
8
8
8
8
12
13
12
13
12
13
12
13
Pulse In
Pulse Out
15
15
9
9
15
9
15
9
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
8
8
8
8
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
I
inH
I
inL
Output Voltage
Logic 1
V
OH
Output Voltage
Logic 0
V
OL
12
13
Threshold Voltage
Logic 1
V
OHA
Threshold Voltage
Logic 0
V
OLA
Switching Times
Propagation Delay
(50Ω Load)
t
12+15–
t
12–15+
t
12+9+
t
12–9–
(20 to 80%)
(20 to 80%)
t
15+
t
9+
t
15–
t
9–
15
15
9
9
15
9
15
9
12
12
12
12
12
12
12
12
Rise Time
Fall Time
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10102
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
B
–N–
Y BRK
D
–L–
–M–
W
D
X
V
A
Z
R
0.007 (0.180)
0.007 (0.180)
M
0.007 (0.180)
U
M
T L-M
M
S
N
S
S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D–D
T L-M
T L-M
S
N
N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1
K
C
E
0.004 (0.100)
G
G1
0.010 (0.250)
S
T L-M
J
–T–
SEATING
PLANE
F
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
---
0.025
---
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
---
0.020
2
_
10
_
0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
---
0.64
---
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
---
0.50
2
_
10
_
7.88
8.38
1.02
---
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