liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
03/18/2008
1
IS24C02C
FUNCTIONAL BLOCK DIAGRAM
Vcc
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
SDA
WP
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
A1
A2
WORD ADDRESS
COUNTER
X
DECODER
SCL
CONTROL
LOGIC
00H-7FH
ARRAY
80H-FFH
Y
DECODER
GND
nMOS
ACK
Clock
DI/O
>
DATA
REGISTER
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
03/18/2008
IS24C02C
PIN CONFIGURATION
8-Pin TSSOP
8-Pin SOIC, PDIP, MSOP
8-pad DFN
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0 1
A1 2
A2 3
GND
4
8 VCC
7
WP
6
SCL
5
SDA
(Top View)
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software write-
protection cannot be initiated. When WP is tied to GND
or left floating, normal read/write operations are allowed
to the device. If the device has already received a write-
protection command, the memory in the range of 00h-7Fh
is read -only regardless of the setting of the WP pin.
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
DEVICE OPERATION
The IS24C02C features a serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I
2
C
TM
.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an
open drain output and can be wire Or'ed with other open
drain or open collector outputs. The SDA bus requires
a
pullup resistor to Vcc.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and
the receiving device as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C02C is the Slave device on the bus.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that
are hardwired or left unconnected for hardware flexibility.
When pins are hardwired, as many as eight devices may
be addressed on a single bus system. When the pins are
not hardwired, the default values of A0, A1, and A2 are
zero.
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. 00C
03/18/2008
3
IS24C02C
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for normal read/write operations, and
0110 for permanent write-protection operations.
This device has three address bits (A1, A2, and A0) that
allow up to eight IS24C02C devices to share the 2-wire
bus. Upon receiving the Slave address, the device
compares the three address bits with the hardwired
A2, A1, and A0 input pins to determine if it is the
appropriate Slave. If any of the A2 - A0 pins is neither
biased to High nor Low, internal circuitry defaults the
value to Low.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave (eg.
IS24C02C) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The
selected IS24C02C then prepares for a Read or Write
operation by monitoring the bus.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS24C02C monitors the SDA and SCL
lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C02C contains a reset function in case the
2-wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24C02C will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if no write operation is initiated; or c) Following any
internal write operation
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
03/18/2008
IS24C02C
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends a byte address that is written
into the address pointer of the IS24C02C. After receiving
another ACK from the Slave, the Master device transmits
the data byte to be written into the address memory
location. The IS24C02C acknowledges once more and
the Master generates the Stop condition, at which time the
device begins its internal programming cycle. While this
internal cycle is in progress, the device will not respond
to any request from the Master device.
WRITE PROTECTION
Hardware Write Protection
The IS24C02C has two forms of software write protec-
tion and one form of hardware write protection. All are
optional. The hardware write protection is enabled when
the WP input is held High. In this case, the entire array
of the IS24C02C is read-only regardless of the status
of the software protection. The hardware protection is
disabled when the WP input is held Low or is floating. In
this case, the upper half of the array (80h-FFh) can be
modified by a valid Write command, and the lower half
of the array (00h-7Fh) can be modified only if software
write protection has not been enabled.
Page Write
The IS24C02C is capable of 16-byte Page-Write operation.
A Page-Write is initiated in the same manner as a Byte
Write, but instead of terminating the internal Write cycle
after the first data byte is transferred, the Master device can
transmit up to 15 more bytes. After the receipt of each data
byte, the IS24C02C responds immediately with an ACK
on SDA line, and the four lower order data byte address
bits are internally incremented by one, while the higher
order bits of the data byte address remain constant. If a
byte address is incremented from the last byte of a page,
it returns to the first byte of that page. If the Master device
should transmit more than 16 bytes prior to issuing the
Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 16
bytes are received and the Stop condition has been sent
by the Master, the internal programming cycle begins. At
this point, all received data is written to the IS24C02C in a
single Write cycle. All inputs are disabled until completion
of the internal Write cycle.
Reversible Software Write Protection
There is a non-volatile flag for each of the two forms of
software write protection. When the bit value for either
flag or both flags is 1, it is not possible to modify the
contents of the lower 128 bytes of the array (00h-7-
Fh).
If the bit value for both flags is 0, it is possible to
modify this half of the array with a valid Write command,
assuming WP is held Low or is floating. The device is
shipped with both flags cleared. One of those flags is the
Reversible Software Write Protection (RSWP) flag, and
can be changed with the Set RSWP and Clear RSWP
commands. The flag can also be verified without being
changed with a Read SWP command. In order to set,
clear or read the RSWP, the IS24C02C input pins must
be as follows: A0 must be held to an extra high voltage
of VHV (see DC Characteristics), while A2 and A1 must
be set High, Low, or left floating, depending on the de-
sired command (see Figure 5). Once these input condi-
tions are met, a command can be issued to the device.
The reversible software commands are initiated similarly
to a normal byte write operation; however, the slave
device address begins with the bit values 0110. The
next three bits are A2 = 0, A1 = 0 or 1, and A0 = 1, so
that they logically match the values on the input pins. If
the last bit of the slave device address (R/W) is 0, the
RSWP flag can be Cleared or Set. If R/W
is 1, the flag
can be verified with the Read SWP command. Following
this bit, the device responds with either ACK or NoACK,
depending on the exact command and the flag status
(see Table 1: Reversible Instructions). To complete the
Set RSWP or Clear RSWP command, the Master must
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C02C initiates the internal Write cycle. ACK polling
can be initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write operation.
If the IS24C02C is still busy with the Write operation, no
No Acknowledge (NoACK) will be returned. If the
IS24C02C has completed the Write operation, an ACK
will be returned and the host can then proceed with the
next Read or Write operation.
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