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IS61NP25632-133TQI

产品描述ZBT SRAM, 256KX32, 4.2ns, CMOS, PQFP100, TQFP-100
产品类别存储   
文件大小154KB,共20页
制造商Integrated Silicon Solution ( ISSI )
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IS61NP25632-133TQI概述

ZBT SRAM, 256KX32, 4.2ns, CMOS, PQFP100, TQFP-100

IS61NP25632-133TQI规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Integrated Silicon Solution ( ISSI )
零件包装代码QFP
包装说明TQFP-100
针数100
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
Is SamacsysN
最长访问时间4.2 ns
其他特性PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)133 MHz
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e0
长度20 mm
内存密度8388608 bit
内存集成电路类型ZBT SRAM
内存宽度32
功能数量1
端子数量100
字数262144 words
字数代码256000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织256KX32
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)240
电源3.3 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.02 A
最小待机电流3.14 V
最大压摆率0.31 mA
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度14 mm
Base Number Matches1

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IS61NP25632 IS61NP25636 IS61NP51218
IS61NLP25632 IS61NLP25636 IS61NLP51218
256K x 32, 256K x 36 and 512K x 18
PIPELINE 'NO WAIT' STATE BUS SRAM
ISSI
®
PRELIMINARY INFORMATION
APRIL 2001
FEATURES
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining for TQFP
Power Down mode
Common data inputs and data outputs
CKE
pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 119 PBGA package
Single +3.3V power supply (± 5%)
NP Version: 3.3V I/O Supply Voltage
NLP Version: 2.5V I/O Supply Voltage
Industrial temperature available
DESCRIPTION
The 8 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 262,144 words by 32 bits, 262,144 words
by 36 bits and 524,288 words by 18 bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE
is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-133
4.2
7.5
133
-100
5
10
100
Units
ns
ns
MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00E
04/26/01
1
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