without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
1
IS75V16F128GS32
GENERAL DESCRIPTION
ISSI
®
This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM.
Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152
words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable,
Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be
accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using
LB
or
UB,
respectively.
The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM
programmer.
The flash chips are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the
PSRAM access time is 65ns.
Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on
each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then
immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same
chip, with zero latency.
MCP BLOCK DIAGRAM
V
CCf1
GND
A0-A21
RESET
1
CEf
1
RY/BY1
64-MBIT
Flash Memory
(Flash 1)
V
CCf2
GND
A0-A21
A0-A21
WP/ACC
RESET
2
CEf
2
RY/BY2
32-MBIT
Flash Memory
(Flash 2)
DQ0-DQ15
V
CCr
A0-A20
GND
LB
UB
WE
OE
CE1r
CE2r
PE
32-MBIT
PSRAM
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
IS75V16F128GS32
ISSI
®
PIN CONFIGURATION (128 Mb Flash and 32 Mb PSRAM)
PACKAGE CODE: B 107 BALL FBGA (Top View) (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
RY/
BY2
CEf2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
LB
WP/ACC
WE
A8
A11
NC
A12 A15
A13 A21
A14
PE
NC
A16
A3
A2
A1
A0
CEf1
UB
RESET1
CE2r
A19
A18
RY/
BY1
A20
A17
DU
DU
DU
DU
A9
A10
DQ6
GND
DQ1
OE
DQ9
DQ3
DQ4
DQ13 DQ15
Vccf1
CE1r
DQ0
DQ10
Vccf1
Vccr
DQ12 DQ7 GND
Shared
NC
DQ8
DQ2
DQ11
NC
DQ5 DQ14
NC
NC
NC
NC
NC
NC
Flash Only
NC
RESET2
GND
Vccf2
NC
NC
NC
PSRAM Only
NC
PIN DESCRIPTIONS
A0-A20
A21
DQ0-DQ15
RESET1
RESET2
CE1r,
CE2r
CEf1
CEf2
OE
WE
PE
Address Inputs, Common
Address Input, Both Flash
Data Inputs/Outputs, Common
Reset, Flash1
Reset, Flash2
Chip Enable, PSRAM
Chip Enable, Flash1
Chip Enable, Flash2
Output Enable, Common
Write Enable, Common
Partial Enable, PSRAM
LB
UB
WP/ACC
RY/BY1
RY/BY2
NC
DU
Vccf1
Vccf2
Vccr
GND
Lower-byte Control, PSRAM
Upper-byte Control, PSRAM
Write Protect/Acceleration Pin, Both Flash
Ready/Busy Output , Flash1
Ready/Busy Output , Flash2
No Connection
Do Not Use
Power, Flash1
Power, Flash2
Power, PSRAM
Ground, Common
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
3
IS75V16F128GS32
DEVICE BUS OPERATION
ISSI
H
H
H
L
H
L
H
L
H
H
H
H
X
H
L
H
H
H
H
H
H
L
L
L
L
X
H
H
H
H
H
H
H
H
H
H
H
H
X
X
H
H
H
L
L
H
H
L
H
H
H
X
X
H
H
H
H
H
L
L
H
L
L
L
X
X
X
X
X
X
X
X
X
L
(9)
L
H
L
X
X
X
X
X
X
X
X
X
L
(9)
L
L
H
X
H
H
H
H
X
X
(10)
X
X
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
D
IN
D
IN
D
OUT
D
IN
High-Z
D
IN
X
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
D
IN
D
IN
D
OUT
D
IN
D
IN
High-Z
X
H
H
H
H
H
H
H
H
H
H
H
H
V
ID
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
®
OPERATION
(1,2)
CE
f1
CE
f2
CE1
r CE2r
OE WE LB
s
UB
s
PE
A
21
-A
0
DQ
7
-DQ
0
DQ
15
-DQ
8
RESET1 RESET2 WP
WP/ACC
(12)
Full Standby
Output Disable
(3)
H
H
L
H
Read from FLASH 1
(4)
L
Read from FLASH 2
(4)
H
Write to FLASH 1
L
Write to FLASH 2
Write to PSRAM
H
H
H
H
Read from PSRAM
(5)
H
H Valid
H Valid
H Valid
H Valid
H Valid
H Valid
H Valid
H Valid
X
X
FLASH 1Temporary
Sector Group
X
(6)
Unprotection
FLASH 2 Temporary
Sector Group
X
Unprotection
(6)
FLASH 1
Hardware Reset
FLASH 2
Hardware Reset
Boot Block Sector
Write Protection
PSRAM Power
(7)
Down Program
PSRAM No Read
PSRAM
Power Down
(8)
X
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
H
H
X
H
H
X
H
L
X
H
H
X
H
H
L
X
X
X
X
L
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
L
X
X
X
Valid
High-Z
High-Z
X
High-Z
High-Z
X
L
X
X
H
H
X
X
L
X
H
H
X
X
X
L
X
X
X
High-Z High-Z
High-Z
X
High-Z
X
H Valid
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations except for indicated this column are prohibited.
2. Do not apply
CEf
= VIL,
CE1r
= VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1ms.
4.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
5. PSRAM
LB,UB
control at Read operation is not supported.
6. It is also used for the extended sector group protections.
7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be re-
programmed after regular Read or Write.
8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention
depends on the selection of Power Down Program.
9. Either or both
LB
and
UB
must be Low for PSRAM Read Operation.
10. Can be either VIL or VIH but must be valid before Read or Write.
11. See “ PSRAM Power Down Program Key Table “ located in the next page.
12. Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
IS75V16F128GS32
ABSOLUTE MAXIMUM RATINGS
(1,5)
Rating
Symbol
Tstg
T
A
V
IN
,V
OUT
V
CC
f1,V
CC
f2
V
CC
r
V
IN
V
ACC
Notes:
Parameter
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All Pins
(2)
V
CC
f Supply
(2)
V
CC
r Supply
(2)
RESET1, RESET2
(3)
WP/ACC
(4)
Min.
–55
–30
–0.3
–0.3
–0.3
-0.5
–0.5
Max.
+125
+85
V
CC
+ 0.3
(6)
3.5
3.5
+13.0
+10.5
ISSI
Unit
°C
°C
V
V
V
V
V
®
1. Voltage is defined on the basis of GND = 0 V.
2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot
GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V
CC
f1+ 0.3V , V
CC
f2+ 0.3V
or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to V
CC
f1+ 2.0V , V
CC
f2+ 2.0 V or VCCr + 1.0 V
for periods of up to 20 ns.
3. Minimum DC input voltage on
RESET1
or
RESET2
pin is -0.5 V. During voltage transitions,
RESET1
or
RESET2
pin may
undershoot GND to -2.0 V for periods of up to 20 ns.
The voltage difference between input and supply voltage (VIN-V
CC
f1 or V
CC
f2) does not exceed 9.0 V.
The maximum DC input voltage on the
RESET
pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns.
4. Minimum DC input voltage on
WP/ACC
pin is -0.5 V. During voltage transitions,
WP/ACC
pin may undershoot
GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on
WP/ACC
pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when V
CC
f1 or V
CC
f2 is applied.
5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
6. This Vcc refers to the minimum of V
CC
f1, V
CC
f2, or Vccr .
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
T
A
V
CC
f1,V
CC
f2
V
CC
r
Note:
Voltage is defined on the basis of GND = 0 V.
Parameter
Ambient Temperature
V
CC
f Supply Voltages
V
CC
r Supply Voltages
Min.
–30
2.7
2.7
Max.
+85
3.3
3.3
Unit
°C
V
V
Integrated Silicon Solution, Inc. — www.issi.com —
1>.\YX_GPS\port\c\yu_port_gui.c(79) : error C2039: 'Release' : is not a member of 'IDirectDrawSurface'
1> D:\Program Files\Windows CE Tools\wce500\STANDARDSDK_500\include\A ......
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