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GS8342DT10BGD-450IT: 产品描述QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; 产品类别存储; 文件大小462KB，共29页; 制造商GSI Technology; 官网地址http://www.gsitechnology.com/; 标准

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GS8342DT10BGD-450IT概述

QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8342DT10BGD-450IT规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	GSI Technology
零件包装代码	BGA
包装说明	LBGA, BGA165,11X15,40
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.B
Is Samacsys	N
最长访问时间	0.45 ns
最大时钟频率 (fCLK)	450 MHz
I/O 类型	SEPARATE
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	15 mm
内存密度	37748736 bit
内存集成电路类型	QDR SRAM
内存宽度	9
湿度敏感等级	3
功能数量	1
端子数量	165
字数	4194304 words
字数代码	4000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	4MX9
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA165,11X15,40
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
电源	1.5/1.8,1.8 V
认证状态	Not Qualified
座面最大高度	1.4 mm
最小待机电流	1.7 V
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	13 mm
Base Number Matches	1

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GS8342DT07/10/19/37BD-450/400/350/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

36Mb SigmaQuad-II+

Burst of 4 SRAM

450 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342DT07/10/19/37BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 4M x 8 has a 1M

addressable index).

SigmaQuad™ Family Overview

The GS8342DT07/10/19/37BD are built in compliance with

the SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342DT07/10/19/37BD SigmaQuad SRAMs

Parameter Synopsis

-450

tKHKH

tKHQV

2.22 ns

0.45 ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.01 6/2012

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8342DT10BGD-450IT

GS8342DT10BGD-450IT概述

GS8342DT10BGD-450IT规格参数

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