Pr eli m i nar y
3200DX Field Programmable Gate Arrays
– The System Logic Integrator
™
Family
Fe atur es
High Capacity
Ge ne r al D e s c r ip t i on
The 3200DX, the first device family in Actel’s Integrator™
Series, are the first FPGAs optimized for high-speed,
high-complexity system logic integration. Based on Actel’s
proprietary PLICE antifuse technology and state-of-the-art
0.6-micron double metal CMOS process, the 3200DX offers
a fine-grained, register-rich architecture with the industry’s
fastest embedded dual-port SRAM.
The 3200DX was designed to integrate high performance
system logic functions typically implemented in multiple
CPLDs, PALs, and FPGAs. The 3200DX is the first
programmable logic device to embed dual-port SRAM into
the programmable array. Offering 5 ns access time, the
3200DX provides the fastest embedded SRAM of any
programmable logic device on the market today. This
combination of fast, flexible SRAM blocks with a true
dual-port architecture, allows designers to implement
extremely fast SRAM functions such as FIFOs, LIFOs and
scratchpad memory. The large number of storage elements
can efficiently address applications requiring wide datapath
manipulation and transformation functions such as
telecommunications, networking, DSP and bus interfaces.
The control and decode functions typically implemented in
CPLDs can easily be integrated into the 3200DX by taking
advantage of the wide decode modules.
The 3200DX family is supported by Actel’s Designer Series
3.0 software which provides a seamless integration into any
ASIC design flow. The Designer Series development tools
offer automatic or fixed pin assignments, automatic
placement and routing (with optional manual placement),
•
•
•
•
•
•
•
•
Up to 40,000 logic gates
Up to 4 Kbits dual-port SRAM
Fast wide decode circuitry
Up to 292 User-programmable I/O Pins
200 MHz datapath applications
5 ns Dual-Port SRAM
100 MHz FIFOs
7.5 ns 35-bit Address Decode
High Performance
Ease-of-Integration
• JTAG 1149.1 Boundary Scan Testing
• Synthesis-friendly architecture supports ASIC design
methodologies
• 95–100% logic utilization using automatic Place and
Route Tools
• Deterministic, user-controllable timing via
DirectTime
™
software tools
• Designer Series
™
development tool support including
interfaces to popular design environments such as
Cadence, Escalade, Exemplar Logic, IST, Mentor
Graphics, Synopsys and Viewlogic
• Pin compatible with 1200XL Family
Prod uct Fami ly P rof il e
Device
Capacity
Logic Gates
Dual-Port SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules (64x4 or 32x8)
Clocks
JTAG
User I/O
A3265DX
6,500
N/A
510
475
20
N/A
2
No
126
A32100DX
10,000
2,048
700
662
20
8
6
Yes
156
A32140DX
14,000
N/A
954
912
24
N/A
2
Yes
176
A32200DX
20,000
2,560
1,230
1,184
24
10
6
Yes
206
A32300DX
30,000
3,072
1,888
1,833
28
12
6
Yes
254
A32400DX
40,000
4,096
2,526
2,466
28
16
6
Yes
292
A u g us t 1 9 9 5
1
© 1995 Actel Corporation
timing analysis, user programming, and debug and diagnostic
probe capabilities. In addition, Designer 3.0 provides the
DirectTime™ tool which provides deterministic as well as
controllable timing. DirectTime allows the designer to
specify the performance requirements of individual paths and
system clock(s). Using these specifications, the software will
automatically optimize the placement and routing of the logic
to meet these constraints. Included with Designer 3.0 is
Actel’s ACTgen
™
Macro Builder. ACTgen allows the
designer to quickly build fast, efficient logic functions such
as counters, adders, FIFOs, and RAM.
The Designer Series tools provide designers the capability to
move up to High-Level Description Languages, such as
VHDL and Verilog, or use schematic design entry with
interfaces to most EDA tools. Designer Series 3.0 is
supported on the following development platforms: 386/486
and Pentium PC, Sun‚ and HP‚ workstations. The software
De vice Reso ur ces
provides CAE interfaces to Cadence, Escalade, Exemplar
Logic, IST, Mentor Graphics‚ OrCAD, Synopsys, and
Viewlogic design environments. Additional development
tools are supported through Actel’s Industry Alliance
Program, including DATA I/O (ABEL FPGA) and MINC.
Actel’s FPGAs are an ideal solution for shortening the system
design and development cycle and offers a cost-effective
alternative for low volume production runs. The 3200DX
devices are an excellent choice for integrating logic that is
currently implemented in TTL, PALs, CPLDs and FPGAs.
Some example applications include high-speed controllers
and address decoding, peripheral bus interfaces, DSP, and
co-processor functions.
User I/Os
Device Series
A3265DX
A32100DX
A32140DX
A32200DX
A32300DX
A32400DX
PLCC
84-pin
72
72
—
—
—
—
PQFP
160-pin
125
125
125
—
—
—
PQFP
208-pin
—
156
176
176
—
—
PQFP
240-pin
—
—
—
TBD
TBD
TBD
TQFP
176-pin
126
151
151
—
—
—
BGA
225-pin
—
156
176
TBD
—
—
BGA
313-pin
—
—
—
206
254
TBD
Package Definitions
(Consult your local Actel Sales Representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array
Orde ring I nfo rmati on
A32200
DX –
1
PQ
208
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-Production
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flatpack
TQ = Thin (1.4 mm) Quad Flatpack
RQ = Power Quad Flatpack
BG = Ball Grid Array
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Sub Family
Part Number
2
32 00 D X F ie l d Pro gr a m m a b l e G a te A rra y s – The S ystem Logic Int egrat or ™ Famil y
Pin D esc ri pt ion
CLKA, CLKB
Clock A and Clock B (input)
QCLKA/B,C,D Quadrant Clock (Input/Output)
TTL Clock inputs for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
These four pins are the quadrant clock inputs. When not used
as a register control signal, these pins can function as general
purpose I/O.
SDI
Serial Data Input (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
TCK
Test Clock
Input LOW supply voltage.
I/O
Input/Output (Input, Output)
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
TDI
Test Data In
I/O pin functions as an input, output, three-state or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the ALS software.
MODE
Mode (Input)
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as
an I/O when the JTAG fuse is not programmed.
TDO
Test Data Out
The MODE pin controls the use of multi-function pins
(DCLK, PRA, PRB, SDI, TDO). When the MODE pin is
HIGH, the special functions are active.
NC
No Connection
Serial data output for JTAG instructions and test data. This
pin functions as an I/O when the JTAG fuse is not
programmed.
TMS
Test Mode Select
This pin is not connected to circuitry within the device.
PRA/I/O
Probe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin's probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB/I/O
Probe B (Output)
Serial data input for JTAG test mode. Data is shifted in on the
rising edge of TCLK. This pin functions as an I/O when the
JTAG fuse is not programmed.
V
CC
Supply Voltage (Input)
Input HIGH supply voltage.
Note:
TCK, TDI, TDO, TMS are only available on
devices containing JTAG circuitry.
32 00 DX A r c h it e c t u r al Ov e r v i ew
The 3200DX family architecture is composed of fine-grained
building blocks which produce fast, efficient logic designs.
All devices within the 3200DX family are composed of
Logic Modules, Routing Resources, Clock Networks, and I/O
modules which are the building blocks to design fast logic
designs. In addition, a subset of the device family contains
embedded dual-port SRAM modules which can implement
fast SRAM functions such as FIFOs, LIFOs, and scratchpad
memory.
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
3
Logic Modules
The 3200DX contains three types of logic modules:
combinatorial (C-modules), sequential (S-modules), and
decode (D-modules). Both the C-module and S-module are
identical to the 1200XL family logic modules.
The combinatorial module (shown in Figure 1) implements
the following function:
Y=!S1*!S0*D00+!S1*S0*D01*S1*!S0*D01+S1*S0*D11
where:
S0=A0*B0
S1=A1 + B1
The S-module is designed to implement high-speed flip-flop
functions within a single module. The S-module implements
the same logic function as the C-module followed by a
sequential block. The sequential block can implement either a
D flip-flop or a transparent latch. The S-module can also be
configured as fully transparent so that it can be used to
implement purely combinatorial logic. The function of the
sequential module is determined by the macro selection from
the design library. The available S-module implementations
A0
B0
S0
D00
D00
D10
D11
S1
A1
B1
Y
Figure 1 •
C-module Implementation
are shown in Figure 2.
D-modules are arranged around the periphery of the device
and contain wide decode circuits providing a fast decode
function similar to CPLDs and PALs (Figure 3). This is
D00
D01
D10
D11
S1
Y
S0
CLR
D
Q
OUT
D00
D01
D10
D11
S1
Y
S0
D
GATE
Q
OUT
Up to 7-input function plus D-type flip-flop with clear
Up to 7-input function plus latch
D00
D0
Y
D1
S
D
GATE
CLR
Q
OUT
D01
D10
D11
S1
S0
Y
OUT
Up to 4-input function plus latch with clear
Figure 2 •
S-module Implementations
Up to 8-input function (same as C-module)
4
32 00 D X F ie l d Pro gr a m m a b l e G a te A rra y s – The S ystem Logic Int egrat or ™ Famil y
analogous to the wide-input AND term in a CPLD or PAL
device. The output of the D-module has a programmable
inverter for active HIGH or LOW assertion. The D-module
output is hardwired to an output pin or can be fed back into
the array to be incorporated into other logic.
Dual-Port SRAM Modules
7 inputs
hardwire to I/O
Programmable
inverter
The 3200DX dual-port SRAM modules have been optimized
for synchronous or asynchronous applications. The SRAM
modules are arranged in 256 bit blocks which can be
configured as 32 x 8 or 64 x 4 (refer to Table 1 for the number
of SRAM modules within a particular device). The SRAM
module block structure allows them to be cascaded together
to form user-definable memory spaces. Resources within the
3200DX architecture allow the SRAM modules to be
cascaded together without incurring an additional delay
penalty. A block diagram of the 3200DX dual-port SRAM
block is shown in Figure 4.
The 3200DX SRAM blocks are true dual-port structures
containing independent READ and WRITE logic. The
SRAM blocks contain six bits of read and write addressing
(RDAD[5:0] and WRAD[5:0] respectively) for 64x4 bit
blocks. When configured in byte mode, the highest order
address bits (RDAD5 and WRAD5) are not used. The read
and write ports of the SRAM blocks contain independent
clocks (RCLK and WCLK) with programmable polarities
offering active HIGH or LOW implementation. The write
feedback to array
Figure 3 •
D-Module Implementation
and read ports of the SRAM block have eight data inputs
(WD[7:0]) and eight outputs (RD[7:0]). The SRAM block
outputs are connected to segmented vertical routing tracks.
The 3200DX dual-port SRAM blocks are ideal for
high-speed buffered applications such as DMA controllers
and FIFO and LIFO queues. Actel’s ACTgen Macro Builder
provides the capability to quickly design memory elements,
such as FIFOs, LIFOs, and RAM arrays which can be
included in any 3200DX design. Additionally, unused SRAM
blocks can be used to implement registers for other logic
within the design.
WD[7:0]
Latches
[7:0]
[5:0]
Write
Port
Logic
SRAM Module
32 x 8 or 64 x 4
(256 bits)
Read
Port
Logic
Latches
RDAD[5:0]
WRAD[5:0]
Latches
[5:0]
Read
Logic
LEN
REN
RCLK
MODE
BLKEN
WEN
WCLK
Write
Logic
RD[7:0]
Routing Tracks
Figure 4 •
Dual-Port SRAM Module
5
FPGA/CPLD
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