Preliminary
GS8182S18/36D-330/300/250/200/167/133
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future frequency
scaling
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb
Σ
2x1B2
DDR SigmaSIO-II SRAM
133 MHz–330 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
Because Separate I/O
Σ
2x1B2 RAMs always transfer data in two
packets, A0 is internally set to 0 for the first read or write transfer, and
automatically incremented by 1 for the next transfer. Because the LSB
is tied off internally, the address field of a
Σ
2x1B2 RAM is always one
address pin less than the advertised index depth (e.g., the 1M x 18
has a 512K addressable index).
- 330
tKHKH
tKHQV
3.0 ns
-300
3.3 ns
-250
4.0 ns
-200
5.0 ns
-167
6.0 ns
0.5 ns
-133
7.5 ns
0.5 ns
0.45 ns 0.45 ns .045 ns 0.45 ns
SigmaRAM™ Family Overview
GS8182S18/36 are built in compliance with the SigmaSIO-II SRAM
pinout standard for Separate I/O synchronous SRAMs. They are
18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide,
very low voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance networking
systems.
Alternating Read-Write Operations
SigmaSIO-II SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to
interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and
re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state
information with command inputs. See the Truth Table for details.
single input register clock input, K. The device also allows the user to
manipulate the output register clock input quasi independently with
the C clock input. If the C clock is tied high, the K clock is routed
internally to fire the output registers instead. Each
Σ
2x1B2
SigmaSIO-II SRAM also supplies an Echo Clock output, CQ, which is
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock output can be used to
fire input registers at the data’s destination.
Clocking and Addressing Schemes
A
Σ
2x1B2 SigmaSIO-II SRAM is a synchronous device. It employs a
Rev: 1.00 4/2003
1/30
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182S18/36D-330/300/250/200/167/133
512K x 36 SigmaQuad SRAM — Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
D
OFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
/SA
(288Mb)
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC/SA
(36Mb)
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW1
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
NC/SA
(36Mb)
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
V
SS
/SA
(144Mb)
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A9 for 36Mb, A3 for 72Mb, A10 for 144Mb, A2 for 288Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 1.00 4/2003
3/30
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182S18/36D-330/300/250/200/167/133
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW1
BW0–BW3
K
MCH
C
MCH
TMS
TDI
TCK
TDO
V
REF
ZQ
K
C
D
OFF
LD
CQ
CQ
MCL
DNU
D0–D35
Q0–Q35
D0–D17
Q0–Q17
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Synchronous Byte Writes
Input Clock
Must Connect High
Output Clock
Must Connect High
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Input Clock
Output Clock
DLL Disable
Synchronous Load Pin
Output Echo Clock
Output Echo Clock
Must Connect Low
Do Not Use
Synchronous Data Inputs
Synchronous Data Outputs
Synchronous Data Inputs
Synchronous Data Outputs
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Output
—
—
Output
Output
—
—
Input
Output
Input
Output
Comments
—
—
Active Low
Active Low
Active Low
x18 Version
Active Low
x36 Version
Active High
DC mode pin
Active High
DC mode pin
—
—
—
—
—
—
Active Low
Active Low
Active Low
Active Low
Active Low
Active High
—
—
x36 Version
x36 Version
x18 Version
x18 Version
Notes:
1. C, C, K, or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left uncon-
nected.
3. NC = Not Connected to die or any other pin
Rev: 1.00 4/2003
4/30
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182S18/36D-330/300/250/200/167/133
Pin Description Table
Symbol
V
DD
V
DDQ
V
SS
Description
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Type
Supply
Supply
Supply
Comments
1.8 V Nominal
1.8 or 1.5 V Nominal
—
Notes:
1. C, C, K, or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left uncon-
nected.
3. NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaSIO-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in
applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM’s bandwidth in half.
A SigmaSIO-II SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM
that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer
protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which
a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs
support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from
differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application
at hand.
Rev: 1.00 4/2003
5/30
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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