One I/O pin can be configured as Output Enable (OE),
Frequency switching (FSEL), Power Down (PDB)
input, or CLK1 output.
•
<10 A current consumption with PDB active.
•
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
•
Operating temperature range from -40°C to 85°C
•
Available in 6-pin DFN, SOT23, and SC70
GREEN/RoHS
compliant packages.
DESCRIPTION
The PL611s-02 is a low-power, small form factor,
high performance OTP-base programmable
frequency synthesizer and a member of PhaseLink’s
PicoPLL Factory Programmable ‘Quick Turn Clocks.
Designed to fit in a small DFN, SC70, or SOT23
package for a broad range of applications, the
PL611s-02 offers the best phase noise and jitter
performance, and power consumption of its rivals. .
In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output. The power down
feature of PL611s-02, when activated, allows the IC
to consume less than 10 A of power, while its
programming flexibility allows generating any output,
up to 200MHz using a low-cost crystal or reference
input.
PACKAGE PIN CONFIGURATION
GND
XIN/FIN
OE, PDB, FSEL, CLK1
GND
1
2
3
6
5
4
XOUT
VDD
CLK0
611s-02
1
2
3
6
5
4
CLK0
VDD
XOUT
OE, PDB,
FSEL, CLK1
GND
XIN/FIN
PL611s-02
1
2
3
6
5
4
CLK0
VDD
XOUT
PL611s-02
OE, PDB,
FSEL, CLK1
XIN/FIN
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
SC70-
SC70-6L
70
(2.3mmx2.25mmx1.0mm)
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
F
REF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F
VCO
= F
REF
* (2 * M/R)
VCO
P-Counter
(5-bit)
F
OUT
= F
VCO
/ (2 * P)
Programmable Function
CLK0
Programming
Logic
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 1
(Preliminary)
PL611s-02
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
PDB - input
•
FSEL - input
•
CLK1 – output
PACKAGE PIN ASSIGNMENT
Pin Assignment
Name
SOT23
Pin #
SC70
Pin#
DFN
Pin#
Type
Description
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), On-the-Fly
Frequency Switching Selector (FSEL), or CLK1 clock output
This pin has an internal 60K pull up resistor for OE, PDB &
FSEL.
State
0
1 (default)
OE
Tri-State CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Frequency ‘2’
Frequency ‘1’
OE, PDB,
FSEL, CLK1
1
2
2
I/O
GND
XIN, FIN
XOUT
VDD
CLK0
2
3
4
5
6
1
3
4
5
6
3
1
6
5
4
P
I
O
GND connection
Crystal or Reference Clock input pin
Crystal Output pin
Do Not Connect (DNC ) when FIN is present
P
O
VDD connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
(Preliminary)
PL611s-02
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-02 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-02 accepts a fundamental input crystal of 10MHz to 50MHz or
reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 200MHz. This flexible
design allows the PL611s-02 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or
F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-02 are mentioned below:
PLL Programming
The PLL in the PL611s-02 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
VCO
/(2*P)),
F
REF
(Crystal or Ref Clk) output, or F
REF
/(2*P) output.
The output drive level can be programmed to Low
Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is
determined by the Power Supply Voltage; 200MHz at
3.3V, 166MHz at 2.5V and 133MHz at 1.8V.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-02 to have an
additional clock output programmed to one of the
following:
F
REF
- Reference (Crystal or Ref Clk) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-02 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10 A of power. The PDB pin incorporates a 60k
pull up resistor giving a default condition of logic “1”.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-02 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull
up resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 3
(Preliminary)
PL611s-02
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
150
85
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
10
T
S
-65
-40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
CONDITIONS
Fundamental Crystal
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Frequency vs. V
DD
+/-10%
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
MIN.
10
1
0.9
0.1
TYP.
MAX.
50
200
166
133
V
DD
V
DD
200
166
133
2
10
2
2
1.7
1.7
55
UNITS
MHz
MHz
V
pp
V
pp
MHz
MHz
MHz
ms
ns
ms
ppm
ns
ns
%
ps
-2
1.2
1.2
45
50
70
Duty Cycle
PLL Enabled, @ V
DD
/2
Period Jitter, Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 4
(Preliminary)
PL611s-02
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
PLL Off: Supply Current, Dynamic,
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic,
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic
with Loaded CMOS Output
Supply Current, Dynamic, with
Loaded Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
CONDITIONS
@ V
DD
=3.3V,30MHz,
load=15pF
@ V
DD
=2.5V,30MHz,
load=15pF
@ V
DD
=1.8V,30MHz,
load=15pF
@ V
DD
=3.3V,30MHz,
load=15pF
@ V
DD
=2.5V,30MHz,
load=15pF
@ V
DD
=1.8V,30MHz,
load=5pF
When PDB=0
MIN.
TYP.
6.0*
3.9*
2.1*
2.0*
1.6*
0.8*
MAX.
UNITS
mA
mA
mA
mA
mA
mA
<10
1.62
3.63
0.4
V
DD
– 0.4
4
8
16
A
V
V
V
mA
mA
mA
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
Output Current, High Drive
I
OHD
V
OL
= 0.4V, V
OH
= 2.4V
* Note: Please contact PhaseLink, if super low-power is required.
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
Maximum Sustainable Drive Level
Operating Drive Level
Shunt Capacitance
Metal Can Crystal
ESR Max
Small SMD Crystal
Shunt Capacitance
ESR Max
SYMBOL
F
XIN
C
L (xtal)
MIN.
10
8
TYP.
MAX.
50
12
100
UNITS
MHz
pF
µW
µW
pF
pF
30
C0
ESR
C0
ESR
5.5
50
2.5
80
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
