Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
•
Up to 2 programmable clock outputs
•
CMOS output frequency up to 35MHz.
•
Accepts Crystal or Ref Clock input
o
Fundamental Crystal: 10MHz to 30MHz
o
Reference Input: 1MHz to 100MHz
•
Accepts >0.1V reference signal input voltage
•
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
•
Operating temperature range from -40°C to 85°C
•
Available in 6-pin DFN, SC70, and SOT23,
GREEN
/RoHS
compliant packages
DESCRIPTION
The PL611s-06 is a low-power general purpose
frequency synthesizer and a member of PhaseLink’s
Programmable ‘Quick Turn Clock (QTC)’ family.
PhaseLink’s PL611s-06 can generate two system
clock frequencies of up to 35MHz from a 10MHz to
30MHz fundamental crystal or a 1MHz to 100MHz
Reference clock source. The PL611s-06 offers the
best phase noise and jitter performance, and power
consumption of its rivals. Cascading of the ICs to
produce additional clock frequencies is also
supported.
PACKAGE PIN CONFIGURATION
OE, CLK1
GND
PL611s-06
1
2
3
6
5
4
CLK0
VDD
XOUT
GND
XIN, FIN
1
2
3
6
5
4
CLK0
VDD
XOUT
PL611s-06
PL611s-06
PL611s-06
PL611s-06
PL611s-06
PL611s-06
PL611s-06
XIN, FIN
OE, CLK1
GND
1
2
3
6
5
4
XOUT
VDD OE, CLK1
CLK0
XIN, FIN
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
SC70-
SC70-6L
70
(2.3mmx2.25mmx1.0mm)
mmx2 25mmx1 mm)
mmx
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
mmx3 mmx1 35mm)
mm
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
F
REF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F
VCO
= F
REF
* (2 * M/R)
VCO
P-Counter
(5-bit)
F
OUT
= F
VCO
/ (2 * P)
Programmable Function
CLK
Programming
Logic
OE, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 1
(Preliminary)
PL611s-06
Low-Power Programmable Quick Turn Clock
T M
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
CLK1 – output
PACKAGE PIN ASSIGNMENT
Name
Pin Assignment
SOT23
SC70
DFN
Pin #
Pin#
Pin#
1
2
2
Type
Description
This programmable I/O pin can be configured as an
Output Enable (OE) input, or CLK1 output. This pin
has an internal 60K pull up resistor (OE Function
Only).
GND connection
Crystal or Reference input pin
Crystal Output pin
XOUT
VDD
CLK0
4
5
6
4
5
6
6
5
4
O
Do Not Connect (DNC ) when FIN is present
P
O
VDD connection
Programmable Clock Output
OE, CLK1
B
GND
XIN, FIN
2
3
1
3
3
1
P
I
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
(Preliminary)
PL611s-06
Low-Power Programmable Quick Turn Clock
T M
FUNCTIONAL DESCRIPTION
PL611s-06 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-06 accepts a fundamental crystal input of 10MHz to 30MHz or
reference clock input of 1MHz to 100MHz and is capable of producing two outputs up to 35MHz. This flexible
design allows the PL611s-06 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or
F
REF
/2 to CLK0 and/or CLK1. Some of the design features of the PL611s-06 are mentioned below:
PLL Programming
The PLL in the PL611s-06 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of the
PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by the
following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
VCO
/(2*P)),
F
REF
(Crystal or Ref Clk Frequency) output, or F
REF
/2
output. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is 35MHz.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up resistor
giving a default condition of logic “1”.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-06 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference ( Crystal or Ref Clk ) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 3
(Preliminary)
PL611s-06
Low-Power Programmable Quick Turn Clock
T M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
150
85
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
10
T
S
-65
-40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
CONDITIONS
Fundamental Crystal
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Frequency vs. V
DD
+/-10%
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
MIN.
10
1
0.9
0.1
TYP.
MAX.
30
100
V
DD
V
DD
35
2
10
2
2
1.7
1.7
55
UNITS
MHz
MHz
Vpp
V
pp
MHz
MHz
MHz
ms
ns
ms
ppm
ns
ns
%
ps
-2
1.2
1.2
45
50
70
Duty Cycle
PLL Enabled, @ V
DD
/2
Period Jitter,Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10,000 samples)
GND.
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 4
(Preliminary)
PL611s-06
Low-Power Programmable Quick Turn Clock
T M
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
I
OHD
CONDITIONS
@ V
DD
=3.3V, 27MHz,
load=15pF
@ V
DD
=2.5V, 27MHz,
load=15pF
@Vdd=1.8V,27MHz,
load=5pF
When PDB=0
MIN.
TYP.
5.5
3.5
1.8
MAX.
UNITS
mA
mA
mA
<10
1.62
3.63
0.4
V
DD
– 0.4
4
8
16
A
V
V
V
mA
mA
mA
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
* Note: Please contact PhaseLink, if super low-power is required.
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
Maximum Sustainable Drive Level
Operating Drive Level
Metal Can Crystal
Shunt Capacitance
ESR Max
Small SMD Crystal
Shunt Capacitance
ESR Max
C0
ESR
C0
ESR
30
5.5
50
2.5
80
pF
SYMBOL
F
XIN
C
L (xtal)
MIN.
10
8
TYP.
MAX.
30
12
100
UNITS
MHz
pF
µW
µW
pF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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