Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
•
Output frequency up to
o
133MHz @ 1.8V operation
o
166MHz @ 2.5V operation
o
200MHz @ 3.3V operation
•
Offered in Tiny
GREEN/RoHS
compliant packages
o
6-pin DFN (2.0mmx1.3mmx0.6mm)
o
6-pin SC70 (2.3mmx2.25mmx1.0mm)
o
6-pin SOT23 (3.0mmx3.0mmx1.35mm)
•
Input Frequency: 10KHz – 200MHz
•
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
•
Operating temperature range from 0°C to 70°C
DESCRIPTION
The PL611s-15 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL
TM
Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance
applications, the PL611s-15 accepts low frequency
(>10KHz) Reference input and generates up to
200MHz output with the best phase noise, jitter
performance, and power consumption for handheld
devices and notebook applications. Cascading
PL611s-15 with other PicoPLL ICs could result in
producing all required system clocks with specific
savings in board space, power consumption, and
cost.
PACKAGE PIN ASSIGNMENT
VDD
FIN
FIN
GNDA
VDD
1
2
3
6
5
4
LF
GND
CLK0
PL611s-15
1
2
3
6
5
4
LF
GND
CLK0
GNDA
FIN
1
2
3
6
5
4
CLK0
GND
LF
PL611s-15
PL611s-15
GNDA
VDD
DFN-6L
(2.0mmx1.3mmx0.6mm)
SC70-6L
(2.3mmx2.25mmx1.0mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
R-Counter
(7-bit)
M-Counter
(16-bit)
Phase
Detector
Charge
Pump
F
VCO
= F
Ref
* (2* M/R)
VCO
Programmable Function
F
Out
= F
VCO
P-Counter
(4-bit)
/2*P
CLK0
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/06 Page 1
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL
TM
32K Programmable Clock
PACKAGE PIN ASSIGNMENT
Name
VDD
GNDA
FIN
LF
GND
CLK0
SOT
1
2
3
4
5
6
Pin #
SC70
3
2
1
6
5
4
DFN
3
2
1
6
5
4
Type
P
P
I
I
P
O
VDD connection.
Description
Ground connection for Analog Circuitry.
Reference input pin.
Loop Filter input pin.
GND connection
Programmable Clock Output
GUIDELINES FOR EXTERNAL COMPONENT SELECTION
For the optimum performance, accurate external loop filter components must be selected. A general guideline for
selecting these components based on the input frequency is shown in the below table. Please contact PhaseLink
for more accurate component selections.
Input frequency
3MHz ~ 200MHz
300KHz ~ 10MHz
30KHz ~ 1.0MHz
10KHz ~ 100KHz
Capacitor Value
4.7nF
4.7nF
4.7nF
47nF
Resistor Value
2.2KΩ
6.8KΩ
22KΩ
22KΩ
APPLICATION RECOMMENDATIONS FOR PL611s-15
PL611s-15 can accept a reference input >10KHz and produce a clock output in the MHz range, as shown in the
diagram ‘1’, below. However, to save costs in consumer product system designs and for greater area optimization,
it is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-15, as shown
in diagram ‘2’, below.
XIN
REFIN
C1
LF
LPGND
MHZ CLK
(Any Frequency
PL611s-
15
XIN
32.768K
Hz
ASIC
C2
XOUT
XOUT
1.8~3.3V
REFIN
LF
LPGND
MHZ CLK
(Any Frequency)
PL611s-
15
1.8~3.3V
Diagram ‘1’
Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.
Diagram ‘2’
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/06 Page 2
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL
TM
32K Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature
T
S
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
4.6
V
DD
+
0.5
V
DD
+
0.5
UNITS
V
V
V
Year
-
0.5
-
0.5
-
0.5
10
-65
-40
150
85
°C
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS
Input Frequency (FIN)
Output Frequency
Output Frequency
Output Frequency
Settling Time
Input (FIN) Signal Amplitude
Output Rise Time
Output Fall Time
Duty Cycle
CONDITIONS
Reference Clock Input
@ Vdd=3.3V
@ Vdd=2.5V
@ Vdd=1.8V
At power-up (after VDD increases over 1.62V)
Internally AC coupled
15pF Load, 10/90%VDD, High Drive, 3.3V
15pF Load, 90/10%VDD, High Drive, 3.3V
VDD/2
MIN.
10KHz
2.5
2.5
2.5
TYP.
MAX.
200
200
166
133
2
UNITS
MHz
MHz
MHz
MHz
ms
Vpp
ns
ns
%
0.9
1
1
45
50
VDD
1.2
1.2
55
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/06 Page 3
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL
TM
32K Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low drive
Output Current, Standard drive
Output Current, High drive
Short-circuit Current
SYMBOL
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
I
OHD
I
S
CONDITIONS
@Vdd=3.3V,30MHz,
load=15pF
@Vdd=2.5V,30MHz,
load=15pF
@Vdd=1.8V,30MHz,
load=5pF
MIN.
TYP.
6.0
3.9
2.1*
MAX.
UNITS
mA
mA
mA
1.62
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
3.3
3.63
0.4
4
8
16
V
V
V
mA
mA
mA
mA
±50
* Note: Please see PL611s-16 datasheet if lower power is required.
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
-
Keep all the PCB traces to PL611s-15 as short
as possible, as well as keeping all other traces
as far away from it as possible.
-
When a reference input clock is generated from
a crystal (see diagram above), place the
PL611s-15 ‘FIN’ as close as possible to the
‘Xout’ crystal pin. This will reduce the cross-
talk between the reference input and the other
signals.
-
Place the Loop Filter (LF) components as close
to the package pin of PL611s-15 as possible.
-
Place a 0.01µF~0.1µF decoupling capacitor
between VDD and GND, on the component
side of the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will
reduce the signal integrity, causing additional
jitter and phase noise.
-
It is highly recommended to keep the VDD and
GND traces as short as possible.
-
When connecting long traces (> 1 inch) to a
CMOS output, it is important to design the
traces as a transmission line or ‘stripline’, to
avoid reflections or ringing. In this case, the
CMOS output needs to be matched to the trace
impedance. Usually ‘striplines’ are designed
for 50Ω impedance and CMOS outputs usually
have lower than 50Ω impedance so matching
can be achieved by adding a resistor in series
with the CMOS output pin to the ‘stripline’
trace.
-
Please contact PhaseLink for the application
note on how to design outputs driving long
traces or the Gerber files for the PL611s-15
layout.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/06 Page 4
(Preliminary)
PL611s-15
1.8V-3.3V PicoPLL
TM
32K Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6 L
Symbol
A
A1
A2
b
c
D
E
H
L
e
SC70-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
DFN-6L
D1
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Pin1 Dot
E
H
D
A2 A
A1
e
b
C
L
Dimension in MM
Min.
Max.
0.80
1.00
0.00
0.09
0.80
0.91
0.15
0.30
0.08
0.25
1.85
2.25
1.15
1.35
2.00
2.30
0.21
0.41
0.65BSC
Pin1 Dot
E
H
D
A2 A
A1
e
b
C
L
Symbol
A
A1
A3
b
e
D
E
D1
E1
L
Dimension in MM
Min.
Max.
0.50
0.60
0.00
0.05
0.152
0.152
0.15
0.25
0.40BSC
1.25
1.35
1.95
2.05
0.75
0.85
0.95
1.05
0.20
0.30
b
e
Pin 6 ID
Chamfer
E1
E
D
L
Pin1 Dot
A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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