Disabled outputs programmable as HiZ or Active Low.
•
Low current consumption:
o
<1.0mA with 27MHz & 32kHz outputs
o
< 5 A when PDB is activated
•
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
•
Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-19 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
Factory Programmable ‘Quick Turn Clock (QTC)’
family. PhaseLink’s PL611s-19 offers the versatility
of using a single Reference Clock input and
producing up to two (kHz or MHz) system clock
outputs. Designed for low-power applications with
very stringent space requirement, PL611s-19
consumes <1.0mA, while producing 2 distinct
outputs of 27MHz and 32kHz. The power down
feature of PL611s-19, when activated, allows the IC
to consume less than 5 A of power.
PL611s-19 fits in a small DFN, SC70, or SOT23
package. Cascading of the PL611s-19 with other
PhaseLink programmable clocks allow generating
system level clocking requirements, thereby
reducing the overall system implementation cost.
In addition, one programmable I/O pin can be
configured as Power Down (PDB) input, Output
Enable (OE), or Frequency switching (FSEL). CLK1
can be programmed as (CLK0, F
REF
, F
REF
/2) output.
BLOCK DIAGRAM
FIN
F
REF
R-Counter
(5-bit)
M-Counter
(8-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F
VCO
= F
REF
* (2 * M/R)
VCO
P-Counter
(14-bit)
F
OUT
= F
VCO
/ (2 * P)
Programmable Function
CLK [0:1]
Programming
Logic
OE, PDB, FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 1
(Preliminary)
PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock
TM
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 8 bit
R = 5 bit
P = 14 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
•
•
•
•
OE - input
FSEL - input
PDB – input
HiZ or Active Low disabled state
PIN CONFIGURATION AND DESCRIPTION
CLK1
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
VDD
OE, PDB, FSEL
CLK0
CLK1
1
2
3
6
5
4
CLK0
VDD
OE, PDB, FSEL
PL611s-19
1
2
3
6
5
4
CLK0
GND
GND
FIN
VDD
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
PL611s-19
PL611s-19
PL611s-19
PL611s-19
PL611s-19
PL611s-19
PL611s-19
FIN
SC70-
SC70-6L
70
mmx2 25mmx mm)
mmx1
(2.3mmx2.25mmx1.0mm)
SOT23-
SOT23-6L
23
mmx3 mmx1 35mm
mm)
(3.0mmx3.0mmx1.35mm)
Name
CLK1
GND
FIN
Pin Assignment
DFN
SC70
SOT
Pin#
Pin#
Pin #
2
3
1
1
5
3
1
2
3
Type
I/O
P
I
Programmable Clock Output
GND connection
Reference input pin
Description
OE, PDB,
FSEL
6
2
4
O
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or On-the-Fly Frequency Switching
Selector (FSEL). This pin has an internal 60K pull up resistor for OE,
PDB & FSEL.
The OE and PDB features can be programmed to allow the output to float
(Hi Z), or to operate in the ‘Active low’ mode.
VDD
CLK0
5
4
4
6
5
6
P
O
VDD connection
Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE
1
0
N/A
N/A
PDB
N/A
N/A
1
0
Osc.
On
On
On
Off
PLL
On
Off
On
Off
CLK0
On
HiZ or Active Low
On
HiZ or Active Low
CLK1
On
On
On
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
(Preliminary)
PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock
TM
FUNCTIONAL DESCRIPTION
PL611s-19 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-19 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-19 to deliver any PLL
generated frequency, F
REF
(Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-19 are mentioned below:
PLL Programming
The PLL in the PL611s-19 is fully programmable.
The PLL is equipped with an 5-bit input frequency
divider (R-Counter), and an 8-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 14-bit post VCO divider
(P-Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
The output of CLK0 can be configured as the PLL output
(F
VCO
/(2*P)), F
REF
(Ref Clk Frequency) output, or
F
REF
/(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is 125MHz.
Clock Output (CLK1)
The output of CLK1 can be configured as:
F
REF
- Reference ( Ref Clk ) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
When using the OE function CLK1 will remain
“Always On” and will not be disabled when OE is
pulled low. When using the PDB function CLK1 will
be disabled along with CLK0. The output drive level
can be programmed to Low Drive (4mA), Standard
Drive (8mA) or High Drive (16mA). The maximum
output frequency is 125MHz.
Programmable I/O (OE/PDB/FSEL)
The PL611s-19 provides one programmable I/O pin
which can be configured as one of the following
functions:
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable CLK0 clock output by toggling the OE
pin. CLK1 remains active when OE is pulled low.
The OE pin incorporates a 60k pull up resistor
giving a default condition of logic “1”.
The OE feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-19 into “Sleep Mode”. When activated
(logic ‘0’), PDB ‘Disables the PLL, the oscillator
circuitry, counters, and all other active circuitry. In
Power Down mode the IC consumes <5 A of power.
The PDB pin incorporates a 60k pull up resistor
giving a default condition of logic “1”.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-19 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 3
(Preliminary)
PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock
TM
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
150
85
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
10
T
S
-65
-40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V
DD
=3.3V
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC/DC coupled (High Frequency)
Internally AC/DC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
1
0.9
0.1
CONDITIONS
MIN.
TYP.
MAX.
200
166
133
V
DD
V
DD
125
90
65
2
10
UNITS
MHz
Vpp
V
pp
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
PDB Function; Ta=25º C, 15pF Load
Output Rise Time
15pF Load, 10/90% V
DD
, High Drive, 3.3V
Output Fall Time
15pF Load, 90/10% V
DD
, High Drive, 3.3V
Duty Cycle
PLL Enabled, @ V
DD
/2
Period Jitter,Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10K samples)
GND.
* Note: Jitter performance depends on the programming parameters.
45
1.2
1.2
50
70
2
1.7
1.7
55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 4
(Preliminary)
PL611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock
TM
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
PLL Off: Supply Current, Dynamic,
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic,
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic
with Loaded CMOS Output
Supply Current, Dynamic, with
Loaded Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
I
OHD
CONDITIONS
@ V
DD
=3.3V,
load=15pF
@ V
DD
=2.5V,
load=10pF
@ V
DD
=1.8V,
load=5pF
@ V
DD
=3.3V,
load=15pF
@ V
DD
=2.5V,
load=15pF
@ V
DD
=1.8V,
load=15pF
@ V
DD
=1.8V,
load=15pF
When PDB=0
27MHz,
27MHz,
27MHz,
32kHz,
32KMHz,
32kHz,
Hz output,
MIN.
TYP.
4.0
2.7
0.9
0.6
0.5
0.2
0.2
MAX.
UNITS
mA
mA
mA
mA
mA
mA
mA
5
1.62
3.63
0.4
A
V
V
V
mA
mA
mA
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
4
8
16
* Note: Please contact PhaseLink, if super-low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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