Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
Output Frequency up to
o
65MHz @ 1.8V operation
o
9/MHz @ 2.5V operation
o
125MHz @ 3.3V operation
Reference Input Frequency: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
Low current consumption, <10 A when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE), Frequency Switching
(FSEL), or Power Down (PDB) input.
Disabled outputs programmable as HiZ or Active Low.
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from 0°C to 70°C
Available in 6-pin SOT23 & DFN
GREEN/RoHS
Compliant packages
DESCRIPTION
The PL611s-27 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLL
product family. Designed to fit in a small 6-pin DFN,
or 6-pin SOT package for high performance
applications, the PL611s-27 offers very low phase
noise, jitter, and power consumption, while offering 2
clock outputs. The Frequency Switching (FSEL)
capability of PL611s-27 allows for programming two
sets of frequencies, while the power down feature of
PL611s-27, when activated, allows the IC to
consume less than 10 A of power. PL611s-27’s
programming flexibility allows generating any output
using a Reference input signal.
•
•
•
•
•
•
•
•
PACKAGE PIN CONFIGURATION
CLK1
PL611s-27
1
2
3
6
5
4
CLK0
VDD
OE, PDB, FSEL
PL611s-27
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
VDD
CLK0
GND
FIN
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
mmx3 mmx1 35mm)
mm
BLOCK DIAGRAM
FIN
F
ref
R-counter
(8-Bit)
M-counter
(11-Bit)
Phase
Detector
Charge
Pump
Loop
Filter
Fvco= Fref * (2 * M / R)
VCO
P-counter
(5-Bit)
Fout=F
VCO
/(2*P)
CLK1
CLK0
Programmable Function
Programming
Logic
OE, PDB,
FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/25/07 Page 1
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
•
•
•
OE - input
PDB - input
FSEL – input
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
CLK1
GND
FIN
Pin Assignment
DFN
SOT
Pin#
Pin #
2
3
1
1
2
3
Type
O
P
I
Description
Programmable Clock Output
GND connection
Reference input pin
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down (PDB) input or Frequency Switching (FSEL) input. This
pin has an internal 60K pull up resistor.
OE,
PDB,
FSEL
6
4
I
The OE and PDB features can be programmed to allow the output to float
(Hi Z), or to operate in the ‘Active low’ mode.
State
0
1 (default)
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Frequency ‘2’
Frequency ‘1’
VDD
CLK0
5
4
5
6
P
O
VDD connection
Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE
1
0
N/A
N/A
PDB
N/A
N/A
1
0
Osc.
On
On
On
Off
PLL
On
Off
On
Off
CLK0
On
HiZ or Active Low
On
HiZ or Active Low
CLK1
On
On
On
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/25/07 Page 2
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-27 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-27 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 55MHz. This flexible design allows the PL611s-27 to deliver any PLL
generated frequency, F
REF
(Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-27 are mentioned below:
PLL Programming
The PLL in the PL611s-27 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [FOUT = FREF * M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
VCO
/(2*P)),
F
REF
(Ref Clk Frequency) output, or F
REF
/(2*P)
output. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is 125MHz.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-27 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference (Ref Clk) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
When using the OE function CLK1 will remain
“Always On” and will not be disabled when OE is
pulled low. When using the PDB function CLK1 will
be disabled along with CLK0. The output drive level
can be programmed to Low Drive (4mA), Standard
Drive (8mA) or High Drive (16mA). The maximum
output frequency is 125MHz.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
The OE feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-27 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10 A of power. The PDB pin incorporates a 60k
pull up resistor giving a default condition of logic “1”.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-27 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull
up resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/25/07 Page 3
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V
DD
=3.3V
Input (FIN) Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Settling Time
Output Enable Time
Output Rise Time
Output Fall Time
Duty Cycle
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
V
DD
/2
45
1.2
1.2
50
70
0.9
0.1
1
CONDITIONS
MIN.
TYP.
MAX.
200
166
133
V
DD
V
DD
125
90
65
2
10
2
1.7
1.7
55
UNITS
MHz
Vpp
V
pp
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
Period Jitter,Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/25/07 Page 4
(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
Stand By Current, with Loaded
Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
I
OHD
CONDITIONS
@ V
DD
=3.3V, 27MHz,
load=15pF
@ V
DD
=2.5V, 27MHz,
load=15pF
@ V
DD
=1.8V, 27MHz,
load=15pF
When PDB=0
MIN.
TYP.
5.5
3.8
1.8*
MAX.
UNITS
mA
mA
mA
<10
1.62
3.63
0.4
V
DD
– 0.4
4
8
16
A
V
V
V
mA
mA
mA
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
* Note: Please contact PhaseLink, if super low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
