Analog Frequency Multiplier
PL660 and PL663 XO Families
DESCRIPTION
PhaseLink’s Analog Frequency Multipliers
(AFMs) are the industry’s first “Balanced Oscillator”
utilizing analog multiplication of the fundamental
frequency (at double or quadruple frequency),
combined with an attenuation of the fundamental of
the reference crystal, without using a phase-locked
loop (PLL), in CMOS technology.
PhaseLink’s patent pending PL66x family of AFM
products can achieve up to 800 MHz differential
PECL, LVDS, or single-ended CMOS output with
little jitter or phase noise deterioration.
PL66x-xx family of products utilize a low-power
CMOS technology and are housed in
GREEN/
RoHS compliant 16-pin TSSOP and 3x3 QFN
packages.
TM
FEATURES
•
•
•
•
•
Non-PLL frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800 MHz
Low phase noise and jitter (equivalent to fundamental
at the output frequency)
Ultra-low jitter
o
RMS phase jitter < 0.25 ps (12 kHz to 20 MHz)
o
RMS period jitter < 2.5 ps typ.
Low phase noise
o
-145 dBc/Hz @ 100 kHz offset from 155.52 MHz
o
-150 dBc/Hz @ 10 MHz offset from 155.52 MHz
Low input frequency eliminates the need for expensive
crystals
Differential PECL/LVDS, or single-ended CMOS output
Single 2.5V or 3.3V +/- 10% power supply
Optional industrial temperature range (-40°C to +85°C)
Available in 16-pin
GREEN/RoHS
compliant
TSSOP, and
16-pin 3x3 QFN packages.
•
•
•
•
•
•
Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3 overtone crystal)
rd
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 1
Analog Frequency Multiplier
PL660 and PL663 XO Families
L2X
OE
X IN
R
XOUT
O n ly r e q u ir e d in x 4 d e s ig n s
L4X
O s c illa t o r
A m p lif ie r
F re q u e n c y
X2
F re q u e n c y
X4
QBAR
Q
Figure 2: Block Diagram of AFM XO
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while
Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e.
low jitter).
Figure 3: Period Jitter Histogram at 212.5MHz
Analog Frequency Multiplier (2x),
with 106.25 MHz crystal
Figure 4: Spectrum Analysis at 212.5MHz
Analog Frequency Multiplier (2x),
with sub-harmonics below –69 dBc
OE LOGIC SELECTION
OUTPUT
PECL
1
0 (Default)
LVDS or CMOS
1
OESEL
0 (Default)
OE
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Output State
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.]
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 2
Analog Frequency Multiplier
PL660 and PL663 XO Families
PRODUCT SELECTOR GUIDE
FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Part
Number
Input
Frequency
Range
(MHz)
30 - 80
30 - 80
30 - 80
30 - 80
30 - 80
75 - 140
75 - 140
75 - 140
140 - 160
140 - 160
Analog
Frequency
Multiplication
Factor
4
4
2
2
2
2
2
2
2
2
Output
Frequency
Range
(MHz)
120 - 320
120 - 320
60 - 160
60 - 160
60 - 160
150 - 280
150 - 280
150 - 280
280 - 320
280 - 320
Phase Noise at Frequency Offset From Carrier (dBc/Hz)
Output
Type
Carrier
Freq.
(MHz)
155.52
155.52
156.25
156.25
156.25
212.5
212.5
212.5
311.04
311.04
10 Hz
-72
-72
-75
-75
-75
-70
-70
-70
-60
-60
100
Hz
-100
-100
-105
-105
-105
-100
-100
-100
-92
-92
1 KHz
-125
-125
-130
-130
-130
-130
-130
-130
-122
-122
10
KHz
-132
-132
-140
-140
-140
-140
-140
-140
-140
-140
100
KHz
-142
-142
-145
-145
-145
-145
-145
-145
-142
-142
1
MHz
-147
-147
-150
-150
-150
-148
-148
-148
-146
-146
10
MHz
-149
-149
-150
-150
-150
-148
-148
-148
-146
-148
PL660-08
PL660-09
PL663-07
PL663-08
PL663-09
PL663-17
PL663-18
PL663-19
PL663-28
PL663-29
PECL
LVDS
CMOS
PECL
LVDS
CMOS
PECL
LVDS
PECL
LVDS
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
RMS Period
Jitter
(ps)
Peak to Peak
Period Jitter
(ps)
RMS
Accumulated
(L.T.) Jitter (ps)
Phase Jitter
(12 KHz-20MHz)
(ps)
Spectral Specifications / Sub-harmonic Content
(dBc)
Frequency (MHz)
Carrier
Freq.
MHz
(Fc)
155.52
155.52
156.25
156.25
156.25
212.50
212.50
212.50
311.04
311.04
@
-75%
(Fc)
-66
-66
@
-50%
(Fc)
-61
-61
-70
-70
-70
-70
-70
-70
-65
-65
@
-25%
(Fc)
@
+25%
(Fc)
@
+50%
(Fc)
-67
-67
-75
-75
-75
-75
-75
-75
-70
-70
@
+75%
(Fc)
-70
-70
Part
Number
Output
Freq.
(MHz)
Min. Typ. Max. Min. Typ. Max. Min. Typ.
Max.
Min.
Typ.
Max.
PL660-08
PL660-09
PL663-07
PL663-08
PL663-09
PL663-17
PL663-18
PL663-19
PL663-28
PL663-29
155.52
155.52
156.25
156.25
156.25
212.50
212.50
212.50
311.04
311.04
3
3
2
2
2
2.5
2.5
2.5
2.5
2.5
5
5
3
3
3
4
4
4
4
4
21
21
18
18
18
18
18
18
18
18
30
30
20
20
20
20
20
20
20
20
5
5
3
3
3
4
4
4
4
4
0.25
0.25
0.24
0.24
0.24
0.19
0.19
0.19
0.16
0.16
Note:
Wavecrest data 10,000 hits. No Filtering was used in Jitter Calculations.
Agilent E5500 was used for phase jitter measurements.
Spectral specifications were obtained using Agilent E7401A.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 3
Analog Frequency Multiplier
PL660 and PL663 XO Families
BOARD LAYOUT CONSIDERATIONS AND CRYSTAL SPECIFICATIONS
BOARD LAYOUT CONSIDERATIONS
To minimize parasitic effects and improve performance, do the following:
•
Place the crystal as close as possible to the IC.
•
Make the board traces that are connected to the crystal pins symmetrical. The board trace
symmetry is very important, as it reduces the negative parasitic effects to produce clean
frequency multiplication with low jitter.
CRYSTAL SPECIFICATIONS
Crystal
Resonator
Frequency
(F
XIN
)
25~75MHz
CL (xtal)
Mode
Typical
Fundamental or
3rd overtone
Fundamental or
3rd overtone
Fundamental or
3rd overtone
Fundamental or
3rd overtone
Max.
Max.
Max.
ESR(R
E)
C0
C0/C1
Part Number
PL660-08
PL660-09
PL663-07
PL663-08
PL663-09
PL663-17
PL663-18
PL663-19
PL663-28
PL663-29
5 pF
30
Ω
4.5 pF
N.A.
30~80MHz
5 pF
30
Ω
4.5 pF
N.A.
75~140MHz
5 pF
60
Ω
4.0 pF
N.A.
140~200MHz
5 pF
60
Ω
4.0 pF
N.A.
Note:
Non-specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment.
Request detailed crystal specifications from PhaseLink.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 4
Analog Frequency Multiplier
PL660 and PL663 XO Families
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board layout
specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s
evaluation board design. These inductor values provide the user with a starting point to determine the optimum
inductor values. Additional fine-tuning may be required to determine the optimal solution.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software. You
can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet
(named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design,
we recommend to use the parasitic information of their board layout to calculate the optimized inductor values.
Please use the following fine tuning procedure:
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE
- Cinternal = Based on AFM Device
- Cpad = 2.0 pF, Bond pad and its ESD circuitry
- C11 = 0.4 pF, The following amplifier stage
PCB side
- LWB1 = 2 nH, (2 places), Stray inductance
- Cstray = 1.0 pF, Stray capacitance
- L2X (L4X) = 2x or 4x inductor
- C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if
used
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 5
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