The Vishay Siliconix SiC402A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK MLP55-32L pin packages.
The SiC402A/B are capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency and
used to drive external n-channel MOSFETs or other loads.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under-voltage protection, programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC402A/B also provides
an enable input and a power good output.
FEATURES
High efficiency > 95 %
10 A continuous output current capability
Integrated bootstrap switch
Programmable 200 mA LDO with bypass logic
Temperature compensated current limit
All ceramic solution enabled
Pseudo fixed-frequency adaptive on-time control
Programmable input UVLO threshold
Independent enable pin for switcher and LDO
Selectable ultra-sonic power-save mode (SiC402A)
Selectable power-save mode (SiC402B)
Programmable soft-start and soft-shutdown
1 % internal reference voltage
Power good output
Over-voltage and under-voltage protections
PowerCAD simulation software available at
www.vishay.com/power-ics/powercad-list/
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PRODUCT SUMMARY
Input Voltage Range
Output Voltage Range
Operating Frequency
Continuous Output Current
Peak Efficiency
Package
3 V to 28 V
0.6 V to V
IN
x 0.75
a
200 kHz to 1 MHz
10 A
95 %
PowerPAK MLP55-32L
APPLICATIONS
•
•
•
•
•
•
Notebook, desktop, and server computers
Digital HDTV and digital consumer applications
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
Point of load power supplies
Note
a. See “High Output Voltage Operation” section
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
3.3 V
EN/PSV (Tri-State)
LDO_EN
EN\PSV
P
GOOD
P
GOOD
A
GND
V
OUT
ENL
T
ON
I
LIM
32 31 30 29 28 27 26 25
LX
LX
FB
V
OUT
V
DD
A
GND
FBL
V
IN
V
IN
1
2
3
4
5
6
8
10
11
24
LX
LX
P
GND
P
GND
P
GND
P
GND
P
GND
P
GND
V
OUT
PAD 1
A
GND
PAD 3
PAD 2
V
IN
NC
12
LX
13
23
22
21
20
19
18
17
LX
SS
7
BST
NC
14
Typical Application Circuit for SiC402A/B (PowerPAK MLP55-32L)
S14-2048-Rev. C, 13-Oct-14
Document Number: 63729
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P
GND
15
P
GND
V
IN
V
IN
V
IN
16
9
SiC402A, SiC402BCD
www.vishay.com
PIN CONFIGURATION
(Top View)
EN\PSV
P
GOOD
A
GND
ENL
tON
I
LIM
LX
LX
Vishay Siliconix
32 31 30 29 28 27 26 25
FB
V
OUT
VDD
A
GND
FBL
V
IN
SS
BST
1
2
3
4
5
6
7
8
V
IN
10
V
IN
11
NC 12
LX 13
NC 14
P
GND
15
P
GND
16
V
IN
9
PAD 2
V
IN
PAD 1
A
GND
PAD 3
LX
24
23
22
21
20
19
18
17
LX
LX
P
GND
P
GND
P
GND
P
GND
P
GND
P
GND
SiC402A/B Pin Configuration (Top View)
PIN DESCRIPTION
PIN NUMBER
1
2
3
4, 30, PAD 1
5
6, 9 to 11, PAD 2
7
8
12, 14
13
23 to 25, PAD 3
15 to 22
26
27
28
29
31
32
SYMBOL
FB
V
OUT
V
DD
A
GND
FBL
V
IN
SS
BST
NC
LXBST
LX
P
GND
P
GOOD
I
ILIM
LXS
EN/PSV
t
ON
ENL
DESCRIPTION
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from V
OUT
to A
GND
.
Switcher output voltage sense pin - also the input to the internal switch-over between V
OUT
and
V
LDO
. The voltage at this pin must be less than or equal to the voltage at the V
DD
pin.
Bias supply for the IC - when using the internal LDO as a bias power supply, V
DD
is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled.
Analog ground
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from V
DD
to A
GND
.
Input supply voltage
The soft start ramp will be programmed by an internal current source charging a capacitor on this pin.
Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high-side gate drive.
No connection
LX Boost - connect to the BST capacitor.
Switching (phase) node
Power ground
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required.
Current limit sense pin - used to program the current limit by connecting a resistor from I
LIM
to LXS.
LX sense - connects to R
ILIM
Enable/power-save input for the switching regulator - connect to A
GND
to disable the switching
regulator, connect to V
DD
to operate with power-save mode and float to operate in forced
continuous mode.
On-time programming input - set the on-time by connecting through a resistor to A
GND
.
Enable input for the LDO - connect ENL to A
GND
to disable the LDO. Drive with logic signal for logic
control, or program the V
IN
UVLO with a resistor divider between V
IN
, ENL, and A
GND
.
ORDERING INFORMATION
PART NUMBER
SiC402ACD-T1-GE3
SiC402BCD-T1-GE3
SiC402DB
PACKAGE
PowerPAK
MLP55-32L
MARKING
(LINE 1: P/N)
SiC402A
SiC402B
Format:
P/N
II
Fyww
Line 1: Dot
Line 2: P/N
Line 3:
Siliconix
Logo + LOT Code + ESD
Symbol
Line 4: Factory Code + Year Code + Work Week Code
Reference Board
S14-2048-Rev. C, 13-Oct-14
Document Number: 63729
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC402A, SiC402BCD
www.vishay.com
FUNCTIONAL BLOCK DIAGRAM
Vishay Siliconix
NC
NC
SiC402A/B Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
V
IN
V
IN
LX
LX (transient < 100 ns)
V
DD
EN/PSV, P
GOOD
, I
LIM
, SS, V
OUT
, FB, FBL
t
ON
BST
ENL
A
GND
to P
GND
Temperature
Maximum Junction Temperature
Storage Temperature
Power Dissipation
Junction to Ambient Thermal Impedance (R
thJA
)
b
Maximum Power Dissipation
ESD Protection
HBM
CDM
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
CONDITIONS
to P
GND
to V
DD
to P
GND
to P
GND
to P
GND
Reference to A
GND
to P
GND
to LX
to P
GND
LIMITS
-0.3 to +30
-0.4 max.
-0.3 to +30
-2 to +30
-0.3 to +6
-0.3 to +(V
DD
+ 0.3)
-0.3 to +(V
DD
- 1.5)
-0.3 to +6
-0.3 to +35
-0.3 to V
IN
-0.3 to +0.3
150
-65 to 150
UNIT
V
°C
IC section
Ambient temperature = 25 °C
Ambient temperature = 100 °C
50
3.4
1.3
2
1
°C/W
W
kV
S14-2048-Rev. C, 13-Oct-14
Document Number: 63729
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC402A, SiC402BCD
www.vishay.com
Vishay Siliconix
RECOMMENDED OPERATING RANGE
(all voltages referenced to GND = 0 V)
PARAMETER
V
IN
V
DD
to P
GND
V
OUT
Temperature
Operating Junction Temperature
Recommended Ambient Temperature
-40 to 125
-40 to 85
°C
MIN.
3
3
0.6
TYP.
-
-
-
MAX.
28
5.5
V
IN
x 0.75
V
UNIT
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
V
IN
= 12 V, T
A
= +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
T
J
= < 125 °C, V
DD
= +5 V,
typical application circuit
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Supplies
Input Supply Voltage
V
DD
V
IN
UVLO Threshold
a
V
IN
UVLO Hysteresis
V
DD
UVLO Threshold
V
DD
UVLO Hysteresis
V
IN
Supply Current
V
IN
V
DD
V
UVLO
V
UVLO, HYS
V
UVLO
V
UVLO, HYS
I
IN
EN/PSV, ENL = 0 V, V
IN
= 28 V
Standby mode: ENL = V
DD
, EN/PSV = 0 V
EN/PSV, ENL = 0 V
SiC402A, EN/PSV = V5V, no load
(f
SW
= 25 kHz), V
FB
> 0.6 V
b
V
DD
Supply Current
I
DD
SiC402B, EN/PSV = V5V, no load
V
FB
> 0.6 V
b
V
DD
= 5 V, f
SW
= 250 kHz,
EN/PSV = floating, no load
b
V
DD
= 3 V, f
SW
= 250 kHz,
EN/PSV = floating, no load
b
FB On-Time Threshold
Frequency Range
Bootstrap Switch Resistance
Timing
On-Time
Minimum On-Time
b
Minimum Off-Time
b
Soft Start
Soft Start Current
b
Soft Start Voltage
b
3
3
Sensed at ENL pin, rising
Sensed at ENL pin, falling
Measured at V
DD
pin, rising
Measured at V
DD
pin, falling
2.4
2.23
-
2.5
2.4
-
-
-
-
-
-
-
-
0.594
-
-
-
Continuous mode operation V
IN
= 15 V,
V
OUT
= 5 V, f
SW
= 300 kHz, R
tON
= 133 k
V
DD
= 5 V
V
DD
= 3 V
-
-
2.6
2.4
0.25
-
-
0.2
10
160
190
0.3
0.7
8
5
0.600
25
10
28
5.5
2.95
2.57
-
3
2.9
-
20
-
300
-
-
mA
-
-
0.606
1000
-
-
V
kHz
μA
V
Static V
IN
and load
f
sw
Continuous mode operation
Minimum f
SW
, (SiC402A only)
t
ON
t
ON min.
t
OFF min.
999
-
-
-
-
1110
80
250
370
3
1.5
500
-
1220
-
-
-
-
-
-
+3
μA
V
k
mV
ns
I
SS
V
SS
When V
OUT
reaches regulation
-
-
Analog Inputs/Outputs
V
OUT
Input Resistance
Current Sense
Zero-Crossing Detector Threshold Voltage
LX-P
GND
-3
S14-2048-Rev. C, 13-Oct-14
Document Number: 63729
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC402A, SiC402BCD
www.vishay.com
Vishay Siliconix
TEST CONDITIONS UNLESS SPECIFIED
V
IN
= 12 V, T
A
= +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
T
J
= < 125 °C, V
DD
= +5 V,
typical application circuit
Upper limit, V
FB
> internal 600 mV
reference
Lower limit, V
FB
< internal 600 mV
reference
V
DD
= 5 V, C
ss
= 10 nF
V
DD
= 3 V, C
ss
= 10 nF
LIMITS
UNIT
MIN.
TYP.
MAX.
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
Power Good
PG_V
TH_UPPER
Power Good Threshold Voltage
PG_V
TH_LOWER
Start-Up Delay Time
(between PWM enable and P
GOOD
high)
Fault (noise-immunity) Delay Time
b
Leakage Current
Power Good On-Resistance
Fault Protection
Vally Current Limit
c
-
-
-
-
-
-
-
+20
-10
12
7
5
-
10
-
%
-
-
-
-
1
-
ms
μs
μA
PG_T
d
PG_I
CC
PG_I
LK
PG_R
DS-ON
I
LIM
V
DD
= 5 V, R
ILIM
= 4460,
T
J
= 0 °C to +125 °C
V
DD
= 3 V, R
ILIM
= 4460
With respect to A
GND
V
FB
with respect to Internal 600 mV
reference, 8 consecutive clocks
V
FB
with respect to internal 600 mV
reference
V
FB
with respect to internal 600 mV
reference
10 °C hysteresis
8.5
-
-
-10
-
-
-
-
-
1
-
2.2
1
0
-10
-
-1
-
10
8.5
10
0
-25
+10
+20
5
150
-
-
-
-
-
-
10
-
0.75
65
115
200
-
-
2
1.2
11.5
-
-
+10
-
-
-
-
-
-
0.4
5
2
0.4
+10
18
+1
-
-
-
-
+130
+500
-
-
A
μA
mV
I
LIM
Source Current
I
LIM
Comparator Offset Voltage
Output Under-Voltage Fault
Smart Power-Save Protection
Threshold
b
Over-Voltage Protection Threshold
Over-Voltage Fault Delay
b
Over Temperature Shutdown
b
Logic Inputs / Outputs
Logic Input High Voltage
Logic Input Low Voltage
EN/PSV Input for P
SAVE
Operation
b
EN/PSV Input for Forced Continuous
Operation
b
EN/PSV Input for Disabling Switcher
EN/PSV Input Bias Current
ENL Input Bias Current
FBL, FB Input Bias Current
Linear Dropout Regulator
FBL
b
V
ILM-LK
V
OUV_Fault
P
SAVE_VTH
%
t
OV-Delay
T
Shut
V
IH
V
IL
μs
°C
V
DD
= 5 V
V
I
EN
FBL_I
LK
V
LDO ACC
EN/PSV = V
DD
or A
GND
ENL = V
IN
= 28 V
FBL, FB = V
DD
or A
GND
μA
V
LDO Current Limit
LDO_I
LIM
Short-circuit protection,
V
IN
=12 V, V
DD
< 0.75 V
Start-up and foldback, V
IN
= 12 V,
0.75 < V
DD
< 90 % of final V
DD
value
Operating current limit, V
IN
= 12 V,
V
DD
> 90 % of final V
DD
value
-
-
135
-130
-500
-
-
mA
V
LDO
to V
OUT
Switch-Over Threshold
d
V
LDO
to V
OUT
Non-Switch-Over Threshold
d
V
LDO
to V
OUT
Switch-Over Resistance
LDO Drop Out Voltage
e
V
LDO-BPS
V
LDO-NBPS
R
LDO
mV
V
V
OUT
= 5 V
From V
IN
to V
DD,
V
DD
= +5 V,
I
VLDO
= 100 mA
Notes
a. V
IN
UVLO is programmable using a resistor divider from V
IN
to ENL to A
GND
. The ENL voltage is compared to an internal reference.
b. Typical value measured on standard evaluation board.
c. SiC402A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout.
d. The switch-over threshold is the maximum voltage differential between the V
DD
and V
OUT
pins which ensures that V
LDO
will internally
switch-over to V
OUT
. The non-switch-over threshold is the minimum voltage differential between the V
LDO
and V
OUT
pins which ensures that
V
LDO
will not switch-over to V
OUT
.
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
S14-2048-Rev. C, 13-Oct-14
Document Number: 63729
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
