MC74AC161, MC74ACT161,
MC74AC163, MC74ACT163
Synchronous Presettable
Binary Counter
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are
high–speed synchronous modulo–16 binary counters. They are
synchronously presettable for application in programmable dividers
and have two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multistage counters.
The MC74AC161/74ACT161 has an asynchronous Master Reset
input that overrides all other inputs and forces the outputs LOW. The
MC74AC163/74ACT163 has a Synchronous Reset input that
overrides counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
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16
1
DIP–16
N SUFFIX
CASE 648
•
•
•
•
•
Synchronous Counting and Loading
High–Speed Synchronous Expansion
Typical Count Rate of 125 MHz
Outputs Source/Sink 24 mA
′ACT161
and
′ACT163
Have TTL Compatible Inputs
VCC
16
TC
15
Q0
14
Q1
13
Q2
12
Q3
11
CET
10
PE
9
16
1
SO–16
D SUFFIX
CASE 751B
16
1
TSSOP–16
DT SUFFIX
CASE 948F
16
1
1
*R
2
CP
3
P0
4
P1
5
P2
6
P3
7
CEP
8
GND
EIAJ–16
M SUFFIX
CASE 966
Figure 1. Pinout: 16–Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
CEP
CET
CP
MR
SR
P0–P3
PE
Q 0–Q 3
TC
FUNCTION
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
(′161) Asynchronous Master Reset Input
(′163) Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip–Flop Outputs
Terminal Count Output
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2001
1
May, 2001 – Rev. 5
Publication Order Number:
MC74AC161/D
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel loading
and allows all outputs to go LOW on the next rising edge
of CP. A LOW signal on PE overrides counting and allows
information on the Parallel Data (Pn) inputs to be loaded
into the flip–flops on the next rising edge of CP. With PE
and MR (′161) or SR (′163) HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The MC74AC161/ACT161 and MC74AC163/ACT163
use D–type edge–triggered flip–flops and changing the SR,
PE, CEP and CET inputs when the CP is in either state does
not cause errors, provided that the recommended setup and
hold times, with respect to the rising edge of CP, are
observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement
synchronous multistage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Please refer to the MC74AC568 data sheet. The TC output
is subject to decoding spikes due to internal race conditions
and is therefore not recommended for use as a clock or
asynchronous reset for flip–flops, counters or registers.
Logic Equations:
Count Enable = CEP
•
CET
•
PE
TC = Q0
•
Q1
•
Q2
•
Q3
•
CET
PE
CEP
CET
CP
*R
P0 P1 P2 P3
TC
Q0 Q1 Q2 Q3
*MR for
′161
*SR for
′163
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
The MC74AC161/ACT161 and MC74AC163/ACT163
count modulo–16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip–flops are driven in parallel through a clock buffer.
Thus all changes of the Q outputs (except due to Master
Reset of the
′161)
occur as a result of, and synchronous
with, the LOW–to–HIGH transition of the CP input signal.
The circuits have four fundamental modes of operation, in
order of precedence: asynchronous reset (′161),
synchronous reset (′163), parallel load, count–up and hold.
Five control inputs – Master Reset (MR,
′161),
Synchronous Reset (SR,
′163),
Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET) –
determine the mode of operation, as shown in the Mode
MODE SELECT TABLE
*SR
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
Action on the Rising
Clock Edge ( )
Reset (Clear)
Load (Pn
→
Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)
0
15
14
13
12
1
2
3
4
5
6
7
11
10
9
8
*For
′163
only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Figure 3. State Diagram
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
P0
PE
′161
CEP
CET
′163
ONLY
′163
P1
P2
P3
TC
CP
CP
′161
ONLY
D
CD
Q0
CP
CP
Q
D
Q
Q0
DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR
′161
SR
′163
Q0
Q1
Q2
Q3
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 4. Logic Diagram
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
Tstg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC VCC or GND Current per Output Pin
Storage Temperature
Value
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
±50
±50
–65 to +150
Unit
V
V
V
mA
mA
mA
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
VCC @ 3.0 V
tr, tf
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
VCC @ 4.5 V
VCC @ 5.5 V
tr, tf
TJ
TA
IOH
IOL
In ut
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current – High
Output Current – Low
VCC @ 4.5 V
VCC @ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
–
–
–
–
–
–
–40
–
–
Typ
5.0
5.0
–
150
40
25
10
8.0
–
25
–
–
Max
6.0
5.5
VCC
–
–
–
–
ns/V
–
140
85
–24
24
°C
°C
mA
mA
ns/V
V
V
Unit
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC
Symbol
Parameter
VCC
(V)
TA = +25°C
Typ
VIH
Minimum High Level
g
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
g
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
VOL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
IIN
IOLD
IOHD
ICC
Maximum Input
Leakage Current
†Minimum Dynamic
Output C
O t t Current
t
Maximum Q
Quiescent
Supply Current
5.5
55
5.5
5.5
5.5
55
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
–
–
–
0.002
0.001
0.001
–
–
–
–
–
–
–
74AC
TA =
–40°C to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
±0
1
–
–
8.0
80
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
±1
0
75
–75
80
V
VOUT = 0.1 V
or VCC – 0.1 V
VOUT = 0.1 V
or VCC – 0.1 V
IOUT = –50
µA
V
*VIN = VIL or VIH
–12 mA
IOH
–24 mA
–24 mA
IOUT = 50
µA
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
VI = VCC, GND
VOLD = 1.65 V Max
VOHD = 3.85 V Min
VIN = VCC or GND
VIL
V
VOH
V
V
µA
mA
mA
µA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC CHARACTERISTICS
(For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC161
Symbol
Parameter
VCC*
(V)
Min
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Maximum Count
Frequency
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
Propagation Delay
CP to TC
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
CET to TC
Propagation Delay
MR to Qn
Propagation Delay
MR to TC
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
70
110
2.0
1.5
1.5
1.5
3.0
2.0
3.5
2.0
2.0
1.5
2.5
2.0
2.0
1.5
3.5
2.5
TA = +25°C
CL = 50 pF
Typ
111
167
7.0
5.0
7.0
5.0
9.0
6.0
8.5
6.5
5.5
3.5
6.5
5.0
6.0
5.5
10.0
8.5
Max
–
–
12.0
9.0
12.0
9.5
15.0
10.5
14.0
11.0
9.5
6.5
11.0
8.5
12.0
9.5
15.0
13.0
74AC161
TA = –40°C
to +85°C
CL = 50 pF
Min
60
95
1.5
1.0
1.5
1.5
2.5
1.5
2.5
2.0
1.5
1.0
2.0
1.5
1.5
1.5
3.0
2.5
Max
–
–
13.5
9.5
13.0
10.0
16.5
11.5
15.5
11.5
11.0
7.5
12.5
9.5
13.5
10.0
17.5
13.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
3–3
3–6
3–6
3–6
3–6
3–6
3–6
3–6
3–6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
AC CHARACTERISTICS
(For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC163
Symbol
Parameter
VCC*
(V)
Min
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Maximum Count
Frequency
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
Propagation Delay
CP to TC
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
CET to TC
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
70
110
2.0
1.5
1.5
1.5
3.0
2.0
3.5
2.0
2.0
1.5
2.5
2.0
TA = +25°C
CL = 50 pF
Typ
95
140
7.5
5.5
8.5
6.0
9.5
7.0
11.0
8.0
7.5
5.5
8.5
6.0
Max
–
–
12.5
9.0
12.0
9.5
15.0
10.5
14.0
11.0
9.5
6.5
11.0
8.5
74AC163
TA = –40°C
to +85°C
CL = 50 pF
Min
60
95
1.5
1.0
1.5
1.5
2.5
1.5
2.5
2.0
1.5
1.0
2.0
1.5
Max
–
–
13.5
9.5
13.0
10.0
16.5
11.5
15.5
11.5
11.0
7.5
12.5
9.5
MHz
ns
ns
ns
ns
ns
ns
3–3
3–6
3–6
3–6
3–6
3–6
3–6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
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