PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
FEATURES
•
•
100MHz to 200MHz Fundamental or 3
rd
Overtone Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz-1GHz(PLL620-09 only, 8x
multiplier).
CMOS (Standard drive PLL620-07 or Selectable
Drive PLL620-06), PECL (Enable low PLL620-08
or Enable high PLL620-05) or LVDS output
(PLL620-09).
Supports 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL620-06 only available in 3x3mm.
Note: PLL620-07 only available in TSSOP.
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
PLL 620-0x
•
•
•
DNC/
DRIVSEL*
SEL0^
10
DESCRIPTION
The PLL620-0x family of XO IC’s is specifically
designed to work with high frequency fundamental
and third overtone crystals. Their low jitter and low
phase noise performance make them well suited for
high frequency XO requirements. They achieve very
low current into the crystal resulting in better overall
stability.
XIN
XOUT
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
VDD
8
7
6
5
GND
CLKC
VDD
CLKT
PLL620-0x
1
2
3
4
GND
GND
GND
BLOCK DIAGRAM
SEL
OE
PLL
(Phase
Locked
Loop)
^: Internal pull-up
*: PLL620-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
Q
Q
X+
X-
Oscillator
Amplifier
PLL620-08
PLL620-05
PLL620-06
PLL620-07
PLL620-09
0
(Default)
1
0
1
(Default)
Output enabled
Tri-state
Tri-state
Output enabled
PLL by-pass
OE input: Logical states defined by PECL levels for PLL620-08
Logical states defined by CMOS levels for PLL620-05/-06/-
07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 1
GND
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
OE
GND
TSSOP*
Pin number
1, 12
2
3
6
7,8,9, 10, 14
3x3mm QFN*
Pin number
6,11
13
14
16
1,2,3,4,8
Type
P
I
I
I
P
+3.3V power supply.
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
Output enable.
Ground (except pin 12 on PLL620-06: DRIVSEL see below).
PLL620-06 only: Drive Select Input. This pin has an internal
pull-up that will default DRIVSEL to ‘1’ when not connect to
GND. CMOS output of PLL620-06 will be high drive CMOS
when DRIVSEL is set to ‘0’, and will be standard CMOS
otherwise. The pin remains ‘Do Not Connect (DNC)’ for
PLL620-05/07/08/09.
True output PECL (PLL620-08) or LVDS (PLL620-09)
(N/C for PLL620-07)
Complementary output PECL (PLL620-08) or LVDS (PLL620-
09)
(CMOS out for PLL620-07).
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
Description
DRIVSEL**
-
12
I
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
11
13
16
15
5
4
5
7
10
9
15
Not available
O
O
I
I
I
I
*
Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
FREQUENCY SELECTION TABLE
SEL3
0
1
1
1
SEL2
0
0
1
1
SEL1
1
1
1
1
SEL0
1
1
0
1
Fin x 4
Fin x 2
No multiplication
Selected Multiplier
Fin x 8(PLL620-09 only)
Note:
SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 2
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
R
E
CONDITIONS
Fundamental or 3
rd
overtone*
MIN.
100
5
AT cut
5
30
TYP.
MAX.
200
UNITS
MHz
pF
pF
Ω
* Note:
3
r d
overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating.
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
CONDITIONS
PECL/LVDS/CMOS
2.97
45
45
45
50
50
50
±50
MIN.
TYP.
MAX.
100/80/40
3.63
55
55
55
UNITS
mA
V
%
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 3
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-peak
Random Jitter
Integrated jitter RMS at 155MHz
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-peak
Random Jitter
Integrated jitter RMS at 622MHz
CONDITIONS
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.3
11
45
11
24
3
1.6
MAX.
20
27
0.4
49
27
1.8
UNITS
ps
ps
ps
ps
ps
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
155.52MHz
622.08MHz
@10Hz
-75
-75
@100Hz
-95
-95
@1kHz
-125
-110
@10kHz
-140
-125
@100kHz
-145
-120
UNITS
dBc/Hz
6. CMOS Electrical Specifications
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
* Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 4
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
7. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
V
out
= V
DD
or GND
V
DD
= 0V
R
L
= 100
Ω
(see figure)
CONDITIONS
MIN.
247
-50
1.4
0.9
1.125
0
1.1
1.2
3
±1
-5.7
1.375
25
±10
-8
TYP.
355
MAX.
454
50
1.6
UNITS
mV
mV
V
V
V
mV
uA
mA
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 5
FPGA/CPLD
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