The chip accepts crystal or clock inputs ranging from
20 to 30MHz, and produces outputs clocks up to
150MHz at 3.3V.
BLOCK DIAGRAM
Phase
Locked
Loop
CLK
XIN
XOUT
XTAL
OSC
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 1
Preliminary
PLL601-15
Low Phase Noise PLL Clock Multiplier
PIN DESCRIPTIONS
Name
CLK
VDD
XIN
XOUT
GND
Number
5
7,6
1
8
2, 3,4
Type
O
P
I
O
P
3.3V Power Supply.
Description
Clock output from VCO. Equals the input frequency times multiplier.
Crystal input to be connected to 20-30MHz fundamental parallel mode crys-
tal (C
L
=15pF). On chip load capacitors: No external capacitor required.
Crystal Connection.
Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 2
Preliminary
PLL601-15
Low Phase Noise PLL Clock Multiplier
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature
T
S
-65
0
SYMBOL
V
CC
V
I
V
O
MIN.
MAX.
7
V
CC
+
0.5
V
CC
+
0.5
260
150
70
UNITS
V
V
V
°C
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
2. AC Specification
PARAMETERS
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Period jitter RMS
Accumulated jitter RMS
Phase Noise, relative to carrier, 150Mhz(x5)
Phase Noise, relative to carrier, 150Mhz(x5)
Phase Noise, relative to carrier, 150Mhz(x5)
Phase Noise, relative to carrier, 150Mhz(x5)
At 3.3V
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
With capacitive decoupling
between VDD and GND
With capacitive decoupling
between VDD and GND
100Hz offset, 3.3V
1kHz offset, 3.3V
10kHz offset, 3.3V
100kHz offset, 3.3V
45
50
6.4
9.4
-103
-126
-133
-128
CONDITIONS
MIN.
20
TYP.
MAX.
30
150
1.5
1.5
55
UNITS
MHz
MHz
ns
ns
%
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 3
Preliminary
PLL601-15
Low Phase Noise PLL Clock Multiplier
3. DC Specification
PARAMETERS
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage At
CMOS Level
Operating Supply Current
Short-circuit Current
SYMBOL
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
I
DD
I
S
CONDITIONS
MIN.
3.135
2
TYP.
MAX.
3.465
0.8
UNITS
V
V
V
V
V
V
V
V
For XIN pin
For XIN pin
I
OH
= -25mA
I
OL
= 25mA
I
OH
= -8mA
No Load
(VDD/2)
+
1
2.4
VDD/2
VDD/2
(VDD/2)
−
1
0.4
VDD-0.4
35
±120
mA
mA
4. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance
Rating
SYMBOL
F
XIN
C
L
(xtal)
CONDITIONS
Parallel Fundamental Mode
MIN.
20
TYP.
MAX.
30
UNITS
MHz
pF
15
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 4
Preliminary
PLL601-15
Low Phase Noise PLL Clock Multiplier
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
1.27 BSC
Min.
-
0.05
0.19
0.09
2.90
4.30
6.20
0.45
TSSOP
Max.
1.20
0.15
0.30
0.20
3.10
4.50
6.60
0.75
0.65 BSC
A1
B
e
C
L
A
D
E
H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PART NUMBER
PLL601-15 X C
PART NUMBER
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
便携式数字数据采集系统（PDDAS）使用了LabVIEW实时模块和PXI，以控制风洞测试和采集记录来自128个不同通道的空气压力数据 "通过LabVIEW实时模块，可以在各种操作情况下获得采集空气压力数据及向风洞提供反馈控制信号所需的确定性响应时间。" – Dave Scheibenhoffer, G Systems 挑战: 用一个可采集、分析和存储来自下一代喷气式战斗机引擎设计的动...[详细]
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