ispLSI and pLSI 1016E
®
®
High-Density Programmable Logic
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Device for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• pLSI/ispLSI DEVELOPMENT TOOLS
pDS
®
Software
— Easy to Use PC Windows™ Interface
— Boolean Logic Compiler
— Manual Partitioning
— Automatic Place and Route
— Static Timing Table
ispDS+™ Software
— Industry Standard, Third-Party Design
Environments
— Schematic Capture, State Machine, HDL
— Automatic Partitioning and Place and Route
— Comprehensive Logic and Timing Simulation
— PC and Workstation Platforms
Functional Block Diagram
A0
B7
B5
GLB
Output Routing Pool
A2
A3
A4
A5
A6
A7
Logic
Array
D Q
D Q
B4
B3
B2
B1
D Q
Global Routing Pool (GRP)
B0
CLK
Description
The ispLSI and pLSI 1016E are High-Density
Programmable Logic Devices containing 96 Registers,
32 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, one Global OE input pin and
a Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1016E features 5-Volt in-system programming
and in-system diagnostic capabilities. The ispLSI 1016E
offers non-volatile “on-the-fly” reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems. It is architecturally and
parametrically compatible to the pLSI 1016E device, but
multiplexes four input pins to control in-system
programming. A functional superset of the ispLSI and
pLSI 1016 architecture, the ispLSI and pLSI 1016E
devices add a new global output enable pin.
The basic unit of logic on the ispLSI and pLSI 1016E
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1...B7 (see figure 1). There are a total of 16
GLBs in the ispLSI and pLSI 1016E devices. Each GLB
has 18 inputs, a programmable AND/OR/Exclusive OR
array, and four outputs which can be configured to be
either combinatorial or registered. Inputs to the GLB
come from the GRP and dedicated inputs. All of the GLB
outputs are brought back into the GRP so that they can
be connected to the inputs of any other GLB on the
device.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997
1996 ISP Encyclopedia
1016E_04
Output Routing Pool
0139C1-isp
A1
D Q
B6
Specifications
ispLSI and pLSI 1016E
Functional Block Diagram
Figure 1. ispLSI and pLSI 1016E Functional Block Diagram
Generic
Logic Blocks
(GLBs)
GOE 0/IN 3
MODE*/IN 2
B7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
*SDI/IN 0
*SDO/IN 1
A0
A1
B6
I/O 31
I/O 30
I/O 29
I/O 28
Output Routing Pool (ORP)
B5
B4
B3
B2
B1
B0
Output Routing Pool (ORP)
Input Bus
A3
A4
A5
A6
A7
Global
Routing
Pool
(GRP)
lnput Bus
A2
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
Clock
Distribution
Network
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Megablock
*ispEN/NC
* ispLSI 1016E Only
Y0
Y1**
*SCLK/Y2
**Note: Y1 and RESET
are multiplexed
on the same pin
0139B(1a)-isp
The devices also have 32 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
4 mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
and pLSI 1016E device contains two Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI and pLSI 1016E devices are se-
lected using the Clock Distribution Network. Three
dedicated clock pins (Y0, Y1 and Y2) are brought into the
distribution network, and five clock outputs (CLK 0,
CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to
route clocks to the GLBs and I/O cells. The Clock Distri-
bution Network can also be driven from a special clock
GLB (B0 on the ispLSI and pLSI 1016E devices). The
logic of this GLB allows the user to create an internal
clock from a combination of internal signals within the
device.
2
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
Absolute Maximum Ratings
1
Supply Voltage V
CC
................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
MIN.
4.75
4.5
0
2.0
MAX.
5.25
5.5
0.8
V
cc
+1
UNITS
V
V
V
V
Table 2-0005/1016E
V
CC
V
IL
V
IH
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
Y0 Clock Capacitance
TYPICAL
8
12
UNITS
pf
pf
TEST CONDITIONS
V
CC
= 5.0V, V
PIN
= 2.0V
V
CC
= 5.0V, V
PIN
= 2.0V
Table 2-0006/1016E
C
1
C
2
Data Retention Specifications
PARAMETER
Data Retention
ispLSI Erase/Reprogram Cycles
pLSI Erase/Reprogram Cycles
MINIMUM
20
10000
100
MAXIMUM
–
–
–
UNITS
Years
Cycles
Cycles
Table 2-0008/1016E
3
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
-125
-100, -80
1.5V
1.5V
See figure 2
Table 2-0003/1016E
Figure 2. Test Load
≤
2 ns
≤
3 ns
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
Output Load Conditions (see figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
0213a
C
Table 2-0004/1016E
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
Commercial
Industrial
CONDITION
MIN.
–
2.4
–
–
–
–
–
–
–
TYP.
–
–
–
–
–
–
–
90
90
3
MAX. UNITS
0.4
–
-10
10
-150
-150
-200
–
–
V
V
µA
µA
µA
µA
mA
mA
mA
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
Table 2-0007/1016E
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
by tester ground degradation. Guaranteed but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book to estimate maximum
I
CC
.
4
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
TEST
2
PARAMETER
#
COND.
4
DESCRIPTION
1
-125
–
–
125
1
tsu2 + tco1
-100
–
–
100
77
125
7.0
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
4.0
4.0
3.5
0.0
10.0
13.0
–
–
–
–
5.0
–
–
6.0
–
13.5
–
–
–
-80
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15.0
18.5
–
–
–
–
8.0
–
–
9.5
–
17.0
–
20.0
20.0
10.5
10.5
–
–
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
7.5
10.0
–
–
–
–
4.5
–
–
5.5
–
10.0
–
12.0
12.0
7.0
7.0
–
–
–
–
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
1.
2.
3.
4.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
–
–
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Prop. Delay, Worst Case Path
3 Clk. Frequency with Int. Feedback
1
3
84.0
57.0
100
8.5
–
0.0
9.5
–
0.0
–
4 Clk. Frequency with Ext. Feedback
(
)
100
167
5.0
–
0.0
5.5
–
0.0
–
5.0
–
–
–
–
3.0
3.0
0.0
5 Clk. Frequency, Max. Toggle
(
twh + tw1
)
6 GLB Reg. Setup Time before Clk., 4 PT Bypass
7 GLB Reg. Clk. to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk., 4 PT Bypass
9 GLB Reg. Setup Time before Clk.
10 GLB Reg. Clk. to Output Delay
11 GLB Reg. Hold Time after Clk.
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Ext. Sync. Clk. Pulse Duration, High
19 Ext. Sync. Clk. Pulse Duration, Low
21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
10.0
–
15.0
15.0
9.0
9.0
–
–
–
–
–
–
–
5.0
5.0
4.5
0.0
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions Section.
Table 2-0030-16/125,100, 80
5
1996 ISP Encyclopedia
DSP 与 ARM 处理器
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