MOTOROLA
Freescale Semiconductor, Inc.
Order Number: MC88915T/D
Rev 5, 08/2001
SEMICONDUCTOR TECHNICAL DATA
2
55, 70, 100, 133 and 160MHz
Versions
Low Skew CMOS PLL
Clock Drivers, 3-State
Freescale Semiconductor, Inc...
The MC88915T Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance
PC’s and workstations. For a 3.3V version, see the MC88LV915T data
sheet.
LOW SKEW CMOS
The PLL allows the high current, low skew outputs to lock onto a single
PLL CLOCK DRIVER
clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88915T to multiply
a low frequency input clock and distribute it locally at a higher (2X) system
frequency. Multiple 88915’s can lock onto a single reference clock, which
is ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see Figure 7).
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°
phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q F
max
specification. The wiring diagrams in Figure 5
detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios
of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1
and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding
FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low fre-
quency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing
(see detailed description on page 11).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the
OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will
go low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees
a SYNC signal and full 5V V
CC
.
MC88915T
MC88915TFN55
MC88915TFN70
MC88915TFN100
MC88915TFN133
MC88915TFN160
Features
•
Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
•
The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t
PD
specification, which defines the part–to–part skew)
•
Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
•
Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)
•
Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
•
All outputs have
±36
mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs
are TTL–level compatible.
±88mA
I
OL
/I
OH
specifications guarantee 50Ω transmission line switching on the incident edge
•
Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy pur-
poses. All outputs can go into high impedance (3–state) for board test purposes
•
Lock Indicator (LOCK) accuracy indicates a phase–locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
Rev 5
12
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pinout: 28–Lead PLCC
(Top View)
OE/RST V
CC
4
FEEDBACK
REF_SEL
SYNC[0]
V
CC
(AN)
RC1
GND(AN)
SYNC[1]
5
6
7
8
9
10
11
12
13
14
Q0
15
V
CC
16
Q1
17
GND
18
PLL_EN
3
Q5
2
GND
1
Q4
28
V
CC
27
2X_Q
26
25
24
23
22
21
20
19
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
MC88915T
2
Freescale Semiconductor, Inc...
FREQ_SEL GND
FN SUFFIX
PLASTIC PLCC
CASE 776–02
PIN SUMMARY
Pin Name
Num
I/O
Function
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0-4)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
V
CC
,GND
1
1
1
1
1
1
5
1
1
1
1
1
1
11
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Doubles VCO Internal Frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency
÷
2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output Enable/Asynchronous reset (active low)
Disables phase-lock for low freq. testing
Power and ground pins (note pins 8, 10 are
analog" supply pins for internal PLL only)
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
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13
MC88915T
Freescale Semiconductor, Inc.
LOCK
FEEDBACK
SYNC (0)
0
SYNC (1)
1
M
U
X
PHASE/FREQ.
DETECTOR
CHARGE PUMP/LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
2
REF_SEL
0
1
EXTERNAL REC NETWORK
(RC1 Pin)
2x_Q
PLL_EN
MUX
Freescale Semiconductor, Inc...
D
(÷1)
1
DIVIDE
BY TWO
(÷2)
0
M
U
X
D
CP
FREQ_SEL
OE/RST
R
CP
R
Q
Q
Q0
Q
Q1
D
CP
R
Q
Q2
D
CP
R
Q
Q3
D
CP
R
Q
Q4
D
CP
R
Q
Q5
D
CP
R
Q
Q/2
Figure 1. MC88915T Block Diagram
(All Versions)
14
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC88915TFN55 and MC88915TFN70
SYNC INPUT TIMING REQUIREMENTS
Minimum
Symbol
t
RISE/FALL
,SYNC Inputs
t
CYCLE
, SYNC Inputs
Duty Cycle SYNC Inputs
Parameter
Rise/Fall Time, SYNC Inputs
From 0.8 to 2.0V
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
TFN70
—
28.5
1
TFN55
—
36.0
1
50%
±25%
MC88915T
Maximum
3.0
200
2
Unit
ns
ns
2
1. These t
CYCLE
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown
in Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
Freescale Semiconductor, Inc...
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) T
A
=–40° C to +85° C for 55MHz Version; T
A
=0° C to +70° C for 70MHz Version; V
CC
= 5.0 V
±
5%
Symbol
V
IH
V
IL
V
OH
V
OL
I
in
I
CCT
I
OLD
I
OHD
I
CC
I
OZ
1.
2.
3.
4.
Maximum Quiescent Supply
Current (per Package)
Maximum 3–State Leakage Current
Parameter
Minimum High–Level Input
Voltage
Maximum Low–Level Input
Voltage
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
Maximum Input Leakage Current
Maximum I
CC
/Input
Minimum Dynamic Output Current
3
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
V
out
= 0.1 V or V
CC
– 0.1 V
V
in
= V
IH
or V
IL
I
OH
= –36 mA
1
V
in
= V
IH
or V
IL
I
OL
= 36 mA
1
V
I
= V
CC
or GND
V
I
= V
CC
– 2.1 V
V
OLD
= 1.0V Max
V
OHD
= 3.85V Min
V
I
= V
CC
or GND
V
I
= V
IH
or V
IL
;V
O
= V
CC
or GND
V
CC
V
4.75
5.25
4.75
5.25
4.75
5.25
4.75
5.25
5.25
5.25
5.25
5.25
5.25
5.25
Target Limit
2.0
2.0
0.8
0.8
4.01
4.51
0.44
0.44
±1.0
2.0
2
Unit
V
V
V
V
µA
mA
mA
mA
mA
µA
88
–88
1.0
±50
4
I
OL
and I
OH
are 12mA and –12mA respectively for the LOCK output.
The PLL_EN input pin is not guaranteed to meet this specification.
Maximum test duration is 2.0ms, one output loaded at a time.
Specification value for I
OZ
is preliminary, will be finalized upon ‘MC’ status.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
C
IN
C
PD
PD
1
PD
2
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
Parameter
Typical Values
4.5
40
23mW/Output
184mW/Device
57mW/Output
456mW/Device
Unit
pF
pF
mW
mW
Conditions
V
CC
= 5.0 V
V
CC
= 5.0 V
V
CC
= 5.0 V
T = 25°C
V
CC
= 5.0 V
T = 25° C
NOTE: PD
1
and PD
2
mW/Output numbers are for a ‘Q’ output.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
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15
MC88915T
Freescale Semiconductor, Inc.
MC88915TFN55 and MC88915TFN70
(continued)
FREQUENCY SPECIFICATIONS
(T
A
=–40° C to +85° C, V
CC
= 5.0 V
±5%)
Guaranteed Minimum
Symbol
f
max
1
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4,Q5 Output)
TFN70
70
35
TFN55
55
27.5
Unit
MHz
MHz
2
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V
CC
/2.
AC CHARACTERISTICS
(T
A
=–40° C to +85° C, V
CC
= 5.0V
±5%,
Load = 50Ω Terminated to V
CC
/2)
Symbol
t
RISE/FALL
Outputs
t
RISE/FALL
1
2X_Q Output
t
PULSE WIDTH
1
(Q0–Q4, Q5, Q/2)
t
PULSE WIDTH
1
(2X_Q Output)
t
PULSE WIDTH
1
(2X_Q Output)
t
PD
1,3
SYNC F db k
Feedback
Parameter
Rise/Fall Time, All Outputs
(Between 0.2V
CC
and 0.8V
CC
)
Rise/Fall Time Into a 20pF Load, With
Termination Specified in Note
2
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ V
CC
/2
Output Pulse Width:
2X_Q @ 1.5V
Output Pulse Width:
2X_Q @ V
CC
/2
66MHz
50MHz
40MHz
50–65MHz
40–49MHz
66–70MHz
Min
1.0
0.5
0.5t
CYCLE
– 0.5
2
0.5t
CYCLE
– 0.5
2
0.5t
CYCLE
– 1.0
0.5t
CYCLE
– 1.5
0.5t
CYCLE
– 1.0
2
0.5t
CYCLE
– 1.5
0.5t
CYCLE
– 0.5
Max
2.5
1.6
0.5t
CYCLE
+ 0.5
2
0.5t
CYCLE
+ 0.5
2
0.5t
CYCLE
+ 1.0
0.5t
CYCLE
+ 1.5
0.5t
CYCLE
+ 1.0
2
0.5t
CYCLE
+ 1.5
0.5t
CYCLE
+ 0.5
Unit
ns
ns
ns
ns
Condition
Into a 50Ω Load
Terminated to V
CC
/2
t
RISE
: 0.8V – 2.0V
t
FALL
: 2.0V – 0.8V
Into a 50Ω Load
Terminated to V
CC
/2
Must Use Termination
Specified in Note
2
Into a 50Ω Load
Terminated to V
CC
/2
See Note
4
and
Figure 2 f D t il d
Fi
for Detailed
Explanation
Freescale Semiconductor, Inc...
ns
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
(M
d t
d
FEEDBACK Input Pins)
(With 1MΩ from RC1 to An V
CC
)
–1.05
–0.40
ns
(With 1MΩ from RC1 to An GND)
+1.25
t
SKEWr
1,4
(Rising) See Note
5
t
SKEWf
1,4
(Falling)
t
SKEWall
1,4
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
—
+3.25
500
ps
All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
All Outputs Into a
Matched 50Ω Load
Terminated to V
CC
/2
Also Time to LOCK
Indicator High
Measured With the
PLL_EN Pin Low
Measured With the
PLL_EN Pin Low
—
500
ps
—
750
ps
t
LOCK
5
1.0
10
ms
t
PZL
6
t
PHZ
,t
PLZ
6
1.
2.
3.
4.
5.
3.0
3.0
14
14
ns
ns
These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
T
CYCLE
in this spec is 1/Frequency at which the particular output is running.
The T
PD
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
Under equally loaded conditions and at a fixed temperature and voltage.
With V
CC
fully powered–on, and an output properly connected to the FEEDBACK pin. t
LOCK
maximum is with C1 = 0.1µF, t
LOCK
minimum is
with C1 = 0.01µF.
6. The t
PZL
, t
PHZ
, t
PLZ
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
16
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
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