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MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
MC68HC908AP8
Data Sheet
M68HC08
Microcontrollers
MC68HC908AP64
Rev. 4
01/2007
freescale.com
MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
MC68HC908AP8
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
3
Revision History
Date
Revision
Level
Description
15.7.2 ADC Clock Control Register
— Changed “The ADC clock should
be set to between 500kHz and 2MHz” to “The ADC clock should be set
to between 500kHz and 1MHz”
Table 22-4 . DC Electrical Characteristics (5V)
— Updated V
OL
values.
August 2005
3
Table 22-6 . Oscillator Specifications (5V)
and
Table 22-10 . Oscillator
Specifications (3V)
— Corrected internal oscillator clock frequency,
f
ICLK
. Updated crystal oscillator component values C
L
, C
1
, C
2
, R
B
, and
R
S
.
Added MC68HC908AP16/AP8 information throughout.
October 2003
2.5
Section 10. Monitor ROM (MON)
— Corrected RAM address to $60.
Section 24. Electrical Specifications
— Added run and wait I
DD
data for
8MHz at 3V.
August 2003
2.4
Section 24. Electrical Specifications
— Updated stop I
DD
data.
Removed MC68HC908AP16 references throughout.
Table 1-2 . Pin Functions
— Added footnote for V
REG
.
5.3 Configuration Register 1 (CONFIG1)
— Clarified LVIPWRD and
LVIREGD bits.
July 2003
2.3
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode
— Updated
BSC bit behavior.
10.5 ROM-Resident Routines
— Corrected data size limits and control
byte size for EE_READ and EE_WRITE.
Figure 12-2 . Timebase Control Register (TBCR)
— Corrected register
address.
Section 24. Electrical Specifications
— Updated.
Updated for f
NOM
= 125kHz and filter components
in CGM section.
Updated electricals.
Page
Number(s)
254
299
January 2007
4
301, 305
—
167
421
417, 421
—
30
67
125
168–193
207
415
101
415
May 2003
2.2
MC68HC908AP Family Data Sheet, Rev. 4
4
Freescale Semiconductor
FPGA/CPLD
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