September 1996
NDT453N
N-Channel Enhancement Mode Field Effect Transistor
General Description
Power SOT N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
Features
8A, 30V. R
DS(ON)
= 0.028
Ω
@ V
GS
= 10V.
R
DS(ON)
= 0.042
Ω
@ V
GS
= 4.5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
___________________________________________________________________________________________
D
D
G
D
S
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
T
A
= 25°C unless otherwise not
NDT453N
30
±20
(Note 1a)
Units
V
V
A
±8
±15
(Note 1a)
(Note 1b)
(Note 1c)
3
1.3
1.1
-65 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
°C/W
°C/W
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
NDT453N Rev. D1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125°C
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 8.0 A
T
J
= 125°C
V
GS
= 4.5 V, I
D
= 6.7 A
T
J
= 125°C
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
V
GS
= 4.5 V, V
DS
= 5 V
Forward Transconductance
V
DS
= 15 V, I
D
= 8.0 A
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
890
560
190
pF
pF
pF
15
10
14
S
1
0.7
2
1.5
0.022
0.03
0.035
0.047
30
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
3
2.2
0.028
0.045
0.042
0.075
A
V
Ω
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 15 V, I
D
= 8.0 A, V
GS
= 10 V
V
DD
= 25 V, I
D
= 1 A,
V
GEN
= 10 V, R
GEN
= 6
Ω
10
20
40
35
28
4.5
9.5
15
35
50
50
35
ns
ns
ns
ns
nC
nC
nC
NDT453N Rev. D1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
2.3
(Note 2)
Units
A
V
ns
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
S
= 8.0 A
0.8
1.3
100
V
GS
= 0 V, I
S
= 2 A, dI
F
/dt = 100A/µs
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 95
o
C/W when mounted on a 0.066 in
2
pad of 2oz copper.
c. 110
o
C/W when mounted on a 0.0123 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT453N Rev. D1
Typical Electrical Characteristics
25
3.5
V
I
D
, DRAIN-SOURCE CURRENT (A)
20
GS
=10V
6.0 5.0
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 3.5V
4.5
R
DS(ON)
, NORMALIZED
3
4.0
2.5
15
4.0
4 .5
2
10
5.0
1.5
3.5
5
1
6.0
7.0
10
3.0
0
0
0.5
1
1.5
2
V
DS
, DRAIN-SOURCE VOLTAGE (V)
2.5
3
0.5
0
5
10
15
20
I
D
, DRAIN CURRENT (A)
25
30
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Gate Voltage and Drain Current.
1.6
2
DRAIN-SOURCE ON-RESISTANCE
I
D
= 8A
1.4
V
GS
= 10 V
DRAIN-SOURCE ON-RESISTANCE
R
DS(on)
, NORMALIZED
V
GS
=10V
R
DS(ON)
, NORMALIZED
1.5
1.2
T J = 125°C
1
25°C
1
0.8
-55°C
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0.5
0
5
10
15
20
I
D
, DRAIN CURRENT (A)
25
30
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
20
GATE-SOURCE THRESHOLD VOLTAGE
1.3
V
DS
= 10V
15
TJ = -55°C
125
25
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
V
DS
= V
GS
I
D
= 250µA
I
D
, DRAIN CURRENT (A)
10
5
0
1
1.5
2
2.5
3
3.5
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
4.5
5
V
th
, NORMALIZED
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDT453N Rev. D1
Typical Electrical Characteristics
(continued)
1.15
DRAIN-SOURCE BREAKDOWN VOLTAGE
20
I
D
= 250µA
I
S
, REVERSE DRAIN CURRENT (A)
1.1
10
5
V
GS
=0V
BV
DSS
, NORMALIZED
1
1.05
TJ = 125°C
25°C
0.1
1
-55°C
0.95
0.01
0.9
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage
Variation with Current and Temperature.
2500
2000
V
GS
, GATE-SOURCE VOLTAGE (V)
1500
1000
CAPACITANCE (pF)
10
I
D
= 8A
C iss
C oss
8
V
DS
= 5V
10V
15V
6
500
4
200
f = 1 MHz
V
GS
= 0V
C rss
2
100
0.1
0
0.2
0.5
1
2
5
10
20
30
0
5
10
15
20
25
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
V
OUT
10%
V
GS
R
GEN
10%
INVERTED
G
DUT
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDT453N Rev. D1
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