MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
ì
High performance, low power flow-through SRAM
ì
Ultra low power for high capacity applications
ì
High performance
ì
66, 83, 100 MHz Speed grades
ì
2-1-1-1 Burst Read
ì
1-1-1-1 Burst Write
ì
2-1-1-1-1-1-1-1... burst operation
ì
Low power
ì
Low active power
ì
Ultra low power ZZ standby mode
ì
Single 3.3V supply (VDD)
ì
Isolated 3.3V or 2.5V I/O supply (VDDQ)
ì
Compatibility
ì
Individual Byte Write and Global Write masking
ì
Interleave and burst address support
ì
Two chip enables for easy expansion
ì
Industry standard 100-Pin SRAM pinout
ì
Industry standard SRAM specification
ì
Applications
ì
Ideal for high speed, low power communica-
tions buffers
ì
Power sensitive portable DSP applications
______________________________________________
Overview
The MoSys MC804256K is a low power flow-through
synchronous SRAM. Fabricated using an advanced low
power, high performance CMOS process, the MoSys
MC804256K is forward pin and function compatible with
standard 32Kx32/36, 64Kx32/36 and 128Kx32/36 SRAM
devices. These devices also include additional operating
features like low power ZZ standby mode and linear
burst order addressing. These additional operating fea-
tures are defined so that, with proper implementation,
designs can work transparently with 32Kx32/36,
64Kx32/36, 128Kx32/36 and 256Kx32/36 configurations.
This allows the designer maximum configuration flexi-
bility within a single footprint layout.
The MoSys MC804256K32/36 supports flow-through
SRAM operating modes at maximum burst frequency
including indefinite pipeline read or write (2-1-1-1-1-1-
1...)
Parameter
Cycle Time
Access Time
Clock to High-Z
Symbol
tKC
tKQ
tKQHZ
-15
15
10
8.6
-12
12
9
7.5
-10
10
8.5
5
Units
ns
ns
ns
The MC804256K is packaged in a standard 100-pin
LQFP.
Lowest Power
The MC804256K flow-through SRAM affords systems
dramatic power savings due to the benefits of its pro-
prietary MoSys technology. Peak operating power of a
typical SRAM is 5x that of the MC804256K. This makes
it ideal for portable applications as well as applications
requiring a large amount of static RAM.
Part Number Designation
Example:
MC804256K32L-15 I
Device Designation:
MC8:,
Series:
04
Organization:
256K32, 256K36
Package Type:
L=LQFP
Speed: – 15
66 MHz
– 12
83 MHz
– 10
100 MHz
Temp:
I
= Industrial Temperature, optional
DS13, Rev 1.2 – 8/25/99
Preliminary Information
LBO#
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC, (DQP3)
DQ17
DQ18
VDDQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VDDQ
DQ23
DQ24
NC
VDD
NC
VSS
DQ25
DQ26
VDDQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VDDQ
DQ31
DQ32
NC, (DQP4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE1#
CE2
BW4#
BW3#
BW2#
BW1#
A17
VDD
VSS
CLK
GW#
BWE#
OE#
ADSC#
ADSP#
ADV#
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 Pin LQFP
20 mm x 14 mm body
0.65 mm nominal pin pitch
NC, (DQP2)
DQ16
DQ15
VDDQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VDDQ
DQ10
DQ9
VSS
NC
VDD
ZZ
DQ8
DQ7
VDDQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VDDQ
DQ2
DQ1
NC, (DQP1)
Figure 1. Pin Function
Page 1
© 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
LBO#
CLK
ADV#
ADSC#
ADSP#
A[17:0]
Binary
Counter
CLK
Q0
CE#
CLR# Q1
18
D
Q
Address
Register
CE#
CLK
16
18
256K x32/36
Memory
Array
GW#
BWE#
BW4#
D
Q
DQ[32:25]
ByteWrite
Registers
CLK
32/36
32/36
D
Q
BW3#
DQ[24:17]
ByteWrite
Registers
CLK
D
Q
BW2#
DQ[16:9]
ByteWrite
Registers
CLK
BW1#
D
Q
DQ[8:1]
CLK
CE1#
CE2
D
Q
Enable
Register
CE#
CLK
4
Input
Register
OE
D
Q
Enable
Delay
Register
CLK
OE#
32/36
DATA[32:1]
Figure 2 Functional Block Diagram
DS13, Rev 1.2 – 8/25/99
Preliminary Information
Page 2
© 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
Table 1. Pin Description
Pin Number
92, 50, 49, 48, 47, 46, 45, 44, 81, 82, 99,
100, 32, 33, 34, 35, 36, 37
96, 95, 94, 93
88
87
89
98
97
86
83
84
85
64
31
29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9,
8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69,
68, 63, 62, 59, 58, 57, 56, 53, 52
30, 1, 80, 51
14, 16, 38, 39, 42, 43, 66
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Symbol
A[17:0]
BW[4:1]#
GW#
BWE#
CLK
CE1#
CE2
OE#
ADV#
ADSP#
ADSC#
ZZ
LBO#
DQ[32:1]
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Description
Host Addresses
Processor host bus byte enables.
Global Write from cache controller
Byte Write Enable from controller
Host bus clock
ADSP# mask and ADSC# chip enable
Depth expansion chip enable
Asynchronous output enable
Burst address counter advance
ADS# of processor
ADS# of controller
Low power sleep mode
Linear Burst Order
Data I/O pins
NC/DQP[4:1]
NC
VDD
VSS
VDDQ
VSSQ
I/O
-
3.3 Volts
Ground
I/O
Supply
I/O
Ground
Data parity I/O pins
unused
Power
Ground
I/O Buffer Supply
I/O Buffer Ground
Table 2. Absolute Maximum Ratings
Symbol
VDD
VDDQ
Vih
Vil
Ts
Parameter
Core Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
VSSQ - 0.5
-65
Min
Max
4.0
VDD
VDDQ +0.5
150
Units
V
V
V
V
°
C
Notes:
Max Vih is not to exceed maximum VDDQ
DS13, Rev 1.2 – 8/25/99
Preliminary Information
Page 3
© 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
Table 3. Recommended Operating Conditions
Symbol
VDD
VDDQ
Vih
Vil
Voh
Vol
TAC
TAI
Parameter
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Commercial Operating Temp.
Industrial Operating Temp.
Ioh = -5 mA
Iol = 5 mA
Condition
3.3V ±5%
2.5V +38%/-5%
Min
3.135
2.375
1.8
-0.3
2.4
0.4
0
-40
70
85
Max
3.465
3.465
VDDQ + 0.3
0.8
Units
V
V
V
V
V
V
°
C
°
C
Table 4. Absolute Maximum AC Operating Conditions
Symbol
Vih
Vil
tOVR
tSET
Parameter
Input High Voltage
Input Low Voltage
Overshoot/Undershoot Voltage Duration
Overshoot/Undershoot Settling Time
Min
1.8
VSSQ
-
1.0
Max
VDDQ+1.0
0.8
0.2*tCY
0.8*tCY
Units
V
V
ns
ns
Table 5. Maximum DC Current Requirements
Symbol
Condition
I
DD
I
DD1
I
DDZ
Operating current, device selected; all inputs < Vil or > Vih; cycle time > tKC min,
VDD= max, 0 pF load
Idle current, device deselected; ADSP#, ADSC#, GW#, BW#s, ADV# and all other
inputs except ZZ > 2.8 volts; cycle time > tKC min, VDD= max, 0 pF load
Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max
Current
50
10
2
Units
mA
mA
mA
DS13, Rev 1.2 – 8/25/99
Preliminary Information
Page 4
© 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
Table 6. AC Timing Characteristics at Recommended Operating Conditions
-10
(100 MHz)
Sym
tAAH
tAAS
tADSH
tADSS
tAH
tAS
tCEH
tCES
tDH
tDS
tKC
tKH
tKL
tKQ
tKQHZ
tKQLZ
tKQX
tOELZ
tOEHZ
tOEQ
tOEQX
tWS
tWH
tZZs
tZZREC
Parameter
ADV# hold
ADV# setup
ADSx# hold
ADSx# setup
Address hold
Address setup
Chip Enable hold
Chip Enable setup
Write Data hold
Write Data setup
Clock cycle
Clock high
Clock low
Clock to output valid
Clock to output high-Z
Clock to output low-Z
Clock to output invalid
OE# to output low-Z
OE# to output high-Z
OE# to output valid
OE# to output invalid
GW#, BWx# setup
GW#, BWx# hold
ZZ standby
ZZ recovery
100
0
2
0.5
100
100
1.5
0
1.5
0
3.5
3.5
0
2
0.5
100
100
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
10
4.5
4.5
8.5
5.0
1.5
0
1.5
0
4.5
4.5
0
2
0.5
100
Max
-12
(83 MHz)
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
12
5.5
5.5
9
7.5
1.5
0
1.5
0
4.8
4.8
Max
-15
(66 MHz)
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
15
6.5
6.5
10
8.6
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS13, Rev 1.2 – 8/25/99
Preliminary Information
Page 5
© 1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
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