SiHD4N80E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
D
FEATURES
• Low figure-of-merit (FOM) R
on
x Q
g
• Low input capacitance (C
iss
)
• Reduced switching and conduction losses
DPAK (TO-252)
D
G
S
G
S
N-Channel MOSFET
• Ultra low gate charge (Q
g
)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
•
•
•
•
PRODUCT SUMMARY
V
DS
(V) at T
J
max.
R
DS(on)
typ. () at 25 °C
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
32
4
6
Single
850
1.1
ORDERING INFORMATION
Package
DPAK (TO-252)
SiHD4N80E-GE3
SiHD4N80ET1-GE3
SiHD4N80ET4-GE3
SiHD4N80ET5-GE3
Lead (Pb)-free and halogen-free
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current (T
J
= 150 °C)
Pulsed drain
Linear derating factor
Single pulse avalanche energy
b
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
Reverse diode dv/dt
d
Soldering recommendations (peak temperature)
c
current
a
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J
, T
stg
T
J
= 125 °C
For 10 s
dv/dt
LIMIT
800
± 30
4.3
2.7
11
0.56
56
69
-55 to +150
70
0.3
300
UNIT
V
A
W/°C
mJ
W
°C
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. V
DD
= 140 V, starting T
J
= 25 °C, L = 28.2 mH, R
g
= 25
,
I
AS
= 2.0 A
c. 1.6 mm from case
d. I
SD
I
D
, di/dt = 100 A/μs, starting T
J
= 25 °C
S19-0414-Rev. B, 06-May-2019
Document Number: 92019
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHD4N80E
www.vishay.com
Vishay Siliconix
SYMBOL
R
thJA
R
thJC
TYP.
-
-
MAX.
62
1.8
UNIT
°C/W
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient
Maximum junction-to-case (drain)
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-source breakdown voltage
V
DS
temperature coefficient
Gate-source threshold Voltage (N)
Gate-source leakage
Zero gate voltage drain current
Drain-source on-state resistance
Forward transconductance
Dynamic
Input capacitance
Output capacitance
Reverse transfer capacitance
Effective output capacitance, energy
related
a
Effective output capacitance, time
related
b
Total gate charge
Gate-source charge
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate input resistance
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
C
o(er)
TEST CONDITIONS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
GS
= ± 30 V
V
DS
= 800 V, V
GS
= 0 V
V
DS
= 640 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 2 A
V
DS
= 30 V, I
D
= 2 A
MIN.
800
-
2.0
-
-
-
-
-
-
-
-
-
-
TYP.
-
1.1
-
-
-
-
-
1.1
1.5
622
34
5
21
91
16
4
6
12
7
26
20
1.2
MAX.
-
-
4.0
± 100
±1
1
10
1.27
-
-
-
-
UNIT
V
V/°C
V
nA
μA
μA
S
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
pF
-
-
32
-
-
24
14
52
40
2.4
ns
nC
V
DS
= 0 V to 480 V, V
GS
= 0 V
C
o(tr)
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
R
g
f = 1 MHz, open drain
V
DD
= 480 V, I
D
= 2 A,
V
GS
= 10 V, R
g
= 9.1
V
GS
= 10 V
I
D
= 2 A, V
DS
= 480 V
-
-
-
-
-
-
-
-
0.6
-
-
-
-
-
-
-
-
-
248
1.4
9.2
4.4
A
11
1.2
496
2.8
-
V
ns
μC
A
G
S
T
J
= 25 °C, I
S
= 2 A, V
GS
= 0 V
T
J
= 25 °C, I
F
= I
S
= 2 A,
di/dt = 100 A/μs, V
R
= 25 V
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 V to 480 V V
DSS
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 V to 480 V V
DSS
S19-0414-Rev. B, 06-May-2019
Document Number: 92019
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHD4N80E
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
12
R
DS(on)
, Drain-to-Source On-Resistance
(Normalized)
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
TOP
Vishay Siliconix
3.0
T
J
= 25 °C
2.5
I
D
= 2 A
I
D
, Drain-to-Source Current (A)
9
2.0
6
1.5
1.0
V
GS
= 10 V
3
0.5
0
0
10
15
V
DS
, Drain-to-Source Voltage (V)
5
20
0
-60 -40 -20
0 20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
6
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
T
J
= 150 °C
10 000
I
D
, Drain-to-Source Current (A)
1000
C, Capacitance (pF)
C
iss
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
4
100
C
oss
10
2
C
rss
0
0
10
15
V
DS
, Drain-to-Source Voltage (V)
5
20
1
0
100
200
300
400
500
V
DS
, Drain-to-Source Voltage (V)
600
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
12
T
J
= 25 °C
I
D
, Drain-to-Source Current (A)
10 000
4.5
4.0
E
oss
, Output Capacitance
Stored
Energy (μJ)
C
oss
, Output Capacitance (pF)
9
3.5
1000
E
oss
C
oss
100
3.0
2.5
2.0
1.5
1.0
T
J
= 150 °C
6
3
0.5
V
DS
= 31.2 V
0
0
5
10
15
V
GS
,
Gate-to-Source
Voltage (V)
20
10
0
100
200
300
400
500
V
DS
, Drain-to-Source Voltage (V)
600
0
Fig. 3 - Typical Transfer Characteristics
S19-0414-Rev. B, 06-May-2019
Fig. 6 - C
oss
and E
oss
vs. V
DS
Document Number: 92019
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHD4N80E
www.vishay.com
Vishay Siliconix
5
12
V
DS
= 480 V
V
DS
= 300 V
V
DS
= 120 V
9
I
D
, Drain Current (A)
0
5
10
15
Q
g
, Total
Gate
Charge (nC)
20
V
GS
,
Gate-to-Source
Voltage (V)
4
3
6
2
3
1
0
0
25
50
75
100
125
T
C
, Case Temperature (°C)
150
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
V
DS
, Drain-to-Source Breakdown Voltage (V)
1050
1025
1000
975
950
925
900
875
850
825
800
775
-60 -40 -20
I
D
= 250 μA
0 20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
I
SD
, Reverse Drain Current (A)
10
1
T
J
= 150 °C
T
J
= 25 °C
V
GS
= 0 V
0.1
0.0
0.3
0.6
0.9
1.2
V
SD
,
Source-Drain
Voltage (V)
1.5
Fig. 8 - Typical Source-Drain Diode Forward Voltage
100
Operation in this area
limited by R
DS(on)
10
I
D
, Drain Current (A)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
I
DM
limited
100 μs
1
Limited by R
DS(on)
*
0.1
T
C
= 25
°C
T
J
= 150 °C
single
pulse
BVDSS limited
1
1 ms
10 ms
0.01
10
100
1000
V
DS
, Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is
specified
Fig. 9 - Maximum Safe Operating Area
S19-0414-Rev. B, 06-May-2019
Document Number: 92019
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHD4N80E
www.vishay.com
Vishay Siliconix
1
Duty cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single
pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
V
DS
V
GS
R
g
R
D
t
p
D.U.T.
+
-
V
DD
V
DS
V
DS
V
DD
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
I
AS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
V
DS
90 %
10 V
Q
gs
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gd
V
G
Charge
Fig. 14 - Switching Time Waveforms
L
V
DS
Vary t
p
to obtain
required I
AS
R
g
D.U.T.
I
AS
10 V
t
p
0.01
Ω
V
GS
3 mA
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same
type as D.U.T.
50 kΩ
+
- V
DD
12 V
0.2 μF
0.3 μF
+
D.U.T.
-
V
DS
Fig. 15 - Unclamped Inductive Test Circuit
I
G
I
D
Current
sampling
resistors
S19-0414-Rev. B, 06-May-2019
Document Number: 92019
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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