XM25QA64A
XM25QA64A
FEATURES
-
-
-
-
-
-
-
-
-
preliminary
64 Megabit 3V Serial Flash Memory with 4Kbyte Uniform Sector
Single power supply operation
Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
SPI Compatible: Mode 0 and Mode 3
64 M-bit Serial Flash
64 M-bit / 8,192 KByte /32,768 pages
256 bytes per programmable page
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO
Dual SPI: CLK, CS#, DQ
0
, DQ
1
Quad SPI: CLK, CS#, DQ
0
, DQ
1
, DQ
2
, DQ
3
Configurable dummy cycle number
High performance
Normal read
- 83MHz
- Fast read
- Standard SPI: 104MHz with 1 dummy bytes
- Dual SPI: 104MHz with 1 dummy bytes
- Quad SPI: 104MHz with 3 dummy bytes
-
-
Write Suspend and Write Resume
Low power consumption
5 mA typical active current
1A typical power down current
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Uniform Sector Architecture:
2048 sectors of 4-Kbyte
256 blocks of 32-Kbyte
128 blocks of 64-Kbyte
Any sector or block can be erased individually
Software and Permanent Protection:
Write Protect all or portion of memory via
software
The Permanent Protection while PPB = 1
Software Reset
High performance program/erase speed
Page program time: 0.5ms typical
Sector erase time: 40ms typical
Half Block erase time 200ms typical
Block erase time 300ms typical
Chip erase time: 32 Seconds typical
Volatile Status Register Bits.
Lockable 512 byte OTP security sector
Read Unique ID Number
Minimum 100K endurance cycle
Data retention time 20 years
Package Options
8 pins SOP 200mil body width
24 balls TFBGA (6x8mm)
All Pb-free packages are compliant RoHS,
Halogen-Free and REACH.
Industrial temperature Range
GENERAL DESCRIPTION
The XM25QA64A is a 64 Megabit (8,192K-byte) Serial Flash memory, with advanced write protection
mechanisms. The XM25QA64A supports the single bit and four bits serial input and output commands
via standard Serial Peripheral Interface (SPI) pins: Serial Clock, Chip Select, Serial DQ
0
(DI) and
DQ
1
(DO), DQ
2
(NC) and DQ
3
(NC). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 416MHz (104Mhz x 4) for Quad Output while using the Quad Output Read
instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The XM25QA64A also offers a sophisticated method for protecting individual blocks against erroneous
or malicious program and erase operations. By providing the ability to individually protect and unprotect
blocks, a system can unprotect a specific block to modify its contents while keeping the remaining
blocks of the memory array securely protected. This is useful in applications where program code is
patched or updated on a subroutine or module basis or in applications where data storage segments
need to be modified without running the risk of errant modifications to the program code segments.
The XM25QA64A is designed to allow either single
Sector/Block
at a time or full chip erase operation.
The XM25QA64A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector
or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. B, Issue Date: 2016/08/02
XM25QA64A
preliminary
Table 1. Pin Names
Symbol
CLK
DI (DQ
0
)
DO (DQ
1
)
CS#
NC (DQ
2
)
NC (DQ
3
)
Vcc
Vss
NC
Pin Name
Serial Clock Input
Serial Data Input (Data Input Output 0)
*1
*1
Serial Data Output (Data Input Output 1)
Chip Enable
NC (Data Input Output 2)
NC (Data Input Output 3)
*2
*2
Supply Voltage (2.7-3.6V)
Ground
No Connect
Note:
1. DQ
0
and DQ
1
are used for Dual and Quad instructions.
2. DQ
0
~ DQ
3
are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ
0
, DQ
1
, DQ
2
, DQ
3
)
The XM25QA64A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ
0
, DQ
1
, DQ
2
and DQ
3
) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. B, Issue Date: 2016/08/02
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
