THC63LVDF84C_Rev.1.20_E
THC63LVDF84C
24bit Color LVDS Receiver (Falling Edge Strobe Output)
General Description
The THC63LVDF84C receiver supports wide
temperature range as -40 to +85C, and wide
frequency range as 8 to 112MHz.
The THC63LVDF84C converts the four LVDS data
streams back into 24bits of LVCMOS data with
falling edge clock. At a transmit clock frequency of
112MHz, 24bits of RGB data and 4bits of timing and
control data (HSYNC, VSYNC, DE, etc.) are
transmitted at an effective rate of 3.1Gbps.
Features
½1:7
LVDS to LVCMOS Deserializer
½Operating
Temperature Range : -40 to +85C
½No
Special Start-up Sequence Required
½Spread
Spectrum Clocking Tolerant up to 100kHz
Frequency Modulation and +/-2.5% Deviations
½Pixel
Clock Range: 8 to 112MHz
½56pin
TSSOP Package
½Power
Down Mode
½Falling
Edge Strobe Output
½EU
RoHS Compliant
Application
½Medium
and Small Size Panel
½Security
Camera
½Multi
Function Printer
½Machine
Vision (Frame Grabber Board)
½Medical
Equipment Monitor
Recommended LVDS Transmitter ICs
½THC63LVDM83D
½THC63LVDM87
Block Diagram
THC63LVDF84C
RA +/-
RB +/-
LVDS Inputs
(56 to 784Mbps/ch) RC +/-
RD +/-
7
LVDS to LVCMOS
1:7 Deserializer
RA0-6
RB0-6
LVCMOS Outputs
RC0-6
RD0-6
7
7
7
RCLK +/-
(8 to 112MHz)
PLL
CLKOUT
(8 to 112MHz)
/PDWN
Figure 1. Block Diagram
Copyright©2016 THine Electronics, Inc.
1
THine Electronics, Inc.
Security E
THC63LVDF84C_Rev.1.20_E
Pin Diagram
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDS GND
RA-
RA+
RB-
RB+
LVDS VCC
LVDS GND
RC-
RC+
RCLK-
RCLK+
RD-
RD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
Figure 2. Pin Diagram
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RCLK+,
RCLK-
RA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT
/PDWN
VCC
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
Pin #
10, 9
12, 11
16, 15
20, 19
Direction
Type
Description
LVDS Data Inputs
Input
18, 17
LVDS
LVDS Clock Inputs
27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 6
7, 34, 41, 42, 49, 50, 2
26
25
31, 40, 48, 56
4, 28, 36, 44, 52
13
8, 14, 21
23
22, 24
Output
LVCMOS
Input
Pixel Data Outputs
Pixel Clock Output
H : Normal Operation
L : Power Down (All outputs are pulled to
ground)
Power Supply Pins for LVCMOS outputs
and digital circuitry
Ground Pins for LVCMOS outputs and
digital circuitry
Power Supply Pins for LVDS inputs
Ground Pins for LVDS inputs
Power Supply Pins for PLL circuitry
Ground Pins for PLL circuitry
-
Power
Table 1. Pin Description
Copyright©2016 THine Electronics, Inc.
2
THine Electronics, Inc.
Security E
THC63LVDF84C_Rev.1.20_E
Absolute Maximum Ratings
Parameter
Supply Voltage (VCC, LVDS VCC, PLL VCC)
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25C
Min
-0.3
-0.3
-0.3
-0.3
-
-55
-
-
-
Max
+4.0
VCC + 0.3
VCC + 0.3
VCC + 0.3
+125
+150
+260
10
1.9
Unit
V
V
V
V
C
C
C
sec
W
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Symbol
VCC33
Ta
PCLK
Parameter
All Supply Voltage(VCC, LVDS VCC, PLL VCC)
Operating Ambient Temperature
RCLK and CLKOUT Clock Frequency
Min
3.0
-40
8
Typ
-
+25
-
Max
3.6
+85
112
Unit
V
C
MHz
Table 3. Recommended Operating Conditions
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.
Copyright©2016 THine Electronics, Inc.
3
THine Electronics, Inc.
Security E
THC63LVDF84C_Rev.1.20_E
Equivalent LVDS Input Schematic Diagram
LVDS VCC
Output
Control
LVDS VCC
CMP
LVDS VCC
LVDS +
AMP
LVDS -
Figure 3. LVDS Input Schematic Diagram
Output Control
/PDWN
H
H
H
L
RCLK +/- Input
Valid Clock
Invalid Clock
Open or Hi-z
Don’t Care
LVCMOS Output
Active Clock & Data
Unfixed Clock & Data
All Low
All Low
Table 4. LVCMOS Output Data Control
Copyright©2016 THine Electronics, Inc.
4
THine Electronics, Inc.
Security E
THC63LVDF84C_Rev.1.20_E
Power Consumption
Over recommended operating supply and temperature range unless otherwise specified
Symbol
I
RCCG
Parameter
LVDS Receiver Operating Current
Gray Scale Pattern 16 (Fig.4)
Conditions
CL=8pF, PCLK=65MHz,
VCC33=3.3V
CL=8pF, PCLK=112MHz,
VCC33=3.3V
CL=8pF, PCLK=65MHz,
VCC33=3.3V
CL=8pF, PCLK=112MHz,
VCC33=3.3V
/PDWN=L
Typ*
55
90
90
130
-
Max
70
110
110
160
500
Unit
mA
mA
mA
mA
µA
I
RCCW
LVDS Receiver Operating Current
Worst Case Pattern(Fig.5)
LVDS Receiver
Power Down Current
I
RCCS
*Typ values are at the conditions of Ta = +25ºC
Table 5. Power Consumption
16 Grayscale Pattern
CLKOUT
RA3, RB4, RC5
RA2, RB3, RC4
RA1, RB2, RC3
RA0, RB1, RC2
TA4-6, TB0/5/6
TC0/1/6, TD0-2
TD3-6
Steady State Low
Steady State High
Figure 4. 16 Grayscale Pattern
Worst Case Pattern
CLKOUT
Rx0-6
X=A,B,C,D
Figure 5. Worst Case Pattern
Copyright©2016 THine Electronics, Inc.
5
THine Electronics, Inc.
Security E
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
