THC63LVD1024_Rev.3.02_E
THC63LVD1024
135MHz 67Bits LVDS Receiver
General Description
The THC63LVD1024 receiver is designed to support
Dual Link transmission between Host and Flat Panel
Display up to 1080p/QXGA resolutions. The
THC63LVD1024 converts the LVDS data streams back
into 67bits of CMOS/TTL data with falling edge or ris-
ing edge clock for convenient with a variety of LCD
panel controllers.
In Dual Link, data transmit clock frequency of
135MHz, 67bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 1.1Gbytes per
second.
Features
•
Wide dot clock range suited for TV Signal(480i-
1080p), PC Signal(VGA-QXGA)
Dual LVDS port IN/Dual TTL port Out Mode:
8 - 135MHz(CLKOUT)
Dual LVDS port IN/Single TTL port Out Mode:
40 - 150MHz(CLKOUT)
•
PLL requires No external components
•
Flexible Input/Output mode
1. Single/Dual LVDS port IN /Single/Dual TTL port OUT
•
•
•
•
•
•
•
2. Double Edge output
50% output clock duty cycle
TTL clock edge selectable
TTL clock output timing programmable(3 step)
2 Output data mapping for simplifying PCB layout.
Power down mode
144pin LQFP Exposed PAD
EU RoHS Compliant
Block Diagram
LVDS INPUT
SERIAL TO PARALLEL
RA1 +/-
RB1 +/-
LVDS INPUT
Port1
RC1 +/-
RD1 +/-
RE1 +/-
32
35
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
TTL OUTPUT
Port1
Data Formatter
1) DEMUX
2) MUX
3) DDR
32
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
TTL OUTPUT
Port2
SERIAL TO PARALLEL
RA2 +/-
RB2 +/-
LVDS INPUT
Port2
RC2 +/-
RD2 +/-
RE2 +/-
3
35
Hsync
Vsync
DE
RCLK +/-
(8 to 135MHz)
/PDWN
MODE[2:0]
DK
R/F
OE
MAP
PLL
CLKOUT
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THC63LVD1024_Rev.3.02_E
Pin Diagram
PGND
PVCC
VCC
CONT12
CONT11
DE
VSYNC
HSYNC
B19
B18
GND
VCC
B17
B16
B15
B14
B13
B12
B11
GND
VCC
B10
G19
G18
G17
G16
G15
GND
VCC
G14
G13
G12
G11
G10
R19
R18
LGND
RA1-
RA1+
RB1-
RB1+
LVCC
LGND
RC1-
RC1+
RCLK-
RCLK+
LVCC
LGND
RD1-
RD1+
RE1-
RE1+
LVCC
LGND
RA2-
RA2+
RB2-
RB2+
LVCC
LGND
RC2-
RC2+
LGND
LGND
LVCC
LGND
RD2-
RD2+
RE2-
RE2+
LGND
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
LQFP144
Exposed PAD
Top View
145GND(Exposed PAD)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
R17
GND
VCC
R16
R15
R14
R13
R12
R11
R10
CGND
CVCC
CLKOUT
GND
GND
VCC
CONT22
CONT21
GND
VCC
B29
B28
B27
B26
B25
GND
VCC
B24
B23
B22
B21
B20
G29
GND
VCC
G28
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PGND
PVCC
Reserved
/PDWN
MODE0
MODE1
DK
R/F
OE
MODE2
MAP
VCC
GND
R20
R21
R22
R23
R24
R25
R26
VCC
GND
R27
R28
R29
G20
G21
VCC
VCC
GND
G22
G23
G24
G25
G26
G27
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Security E
THC63LVD1024_Rev.3.02_E
Pin Description
Pin Name
RA1+, RA1-
RB1+, RB1-
RC1+, RC1-
RD1+, RD1-
RE1+, RE1-
RCLK+, RCLK-
RA2+, RA2-
RB2+, RB2-
RC2+, RC2-
RD2+, RD2-
RE2+, RE2-
R19 ~ R10
G19 ~ G10
B19 ~ B10
R29 ~ R20
G29 ~ G20
B29 ~ B20
CONT11,CONT12
CONT21,CONT22
DE
VSYNC
HSYNC
CLKOUT
/PDWN
Pin #
111, 110
113, 112
117, 116
123, 122
125, 124
119, 118
129, 128
131, 130
135, 134
141, 140
143, 142
74 - 72, 69 - 63
86 - 82, 79 - 75
100, 99,
96-90, 87
25-23, 20-14
40, 37 - 31,
27, 26
52 - 48, 45 - 41
104, 105
55, 56
103
102
101
60
4
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
User defined data output
Data Enable Output.
Vsync Output.
Hsync Output.
Clock Output.
Power down and Output Control.(Table1)
H: Normal operation
L: Power down
Pixel Data Mode
.
MODE1
H
H
L
L
MODE0
H
L
H
L
Mode
Single Link (Single-in/Single-out)
Single Link (Single-in/Dual-out)
Dual Link (Dual-in/Single-out)
Dual Link (Dual-in/Dual-out)
Description
The 1st Link. The 1st pixel input data when Dual Link.
LVDS Clock Input.
The 2nd Link. These pins are disabled when Single Link.
The 1st Pixel Data Outputs.
The 2nd Pixel Data Outputs.
MODE1, MODE0
6, 5
IN
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THC63LVD1024_Rev.3.02_E
Pin Description (Continued)
Pin Name
Pin #
Type
Description
Output Clock Delay Timing Select.
t
DOUT
=Output Data Cycle
MODE[1:0]
LL
HH
HL
DK
L
M
H
L
LH
M
H
Offset [ns]
0
t
DOUT
-
–
6 --------------
28
t
DOUT
-
6 --------------
28
DK
7
IN
0
t
DOUT
-
–
7 --------------
28
t
DOUT
-
7 --------------
28
R/F
OE
8
9
IN
IN
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge.
Output Enable.(Table1)
H: Output enable, L: Output disable
DDR function enable.
The use of this function depends on the setting of
MODE<1:0>.
MODE<1:0>=LH(Dual-in/Single-out Mode)
MODE2
10
IN
H: DDR (Double Edge Output) function enable.
L: DDR (Double Edge Output) function disable.
MODE<1:0>=Other
Must be tied to GND
LVDS mapping table select. See Fig9,10 and Table2 - 9.
MAP
Reserved
VCC
11
3
12, 21, 28, 29,
38, 46, 53, 57,
70, 80, 88, 97,
106
13, 22, 30, 39,
47, 54, 58, 59,
71, 81, 89,
98,145
114, 120, 126,
132, 138
109, 115, 121,
127, 133, 136,
137, 139, 144
2, 107
1, 108
61
62
IN
IN
Power
H: Mapping Mode1
L: Mapping Mode2
Must be tied to VCC.
Power Supply Pins for TTL outputs and digital circuitry.
GND
Ground
Ground Pins for TTL outputs and digital circuitry.
LVCC
Power
Power Supply Pins for LVDS inputs.
LGND
PVCC
PGND
CVCC
CGND
Ground
Power
Ground
Power
Ground
Ground Pins for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
Power Supply Pins for TTL output of CLKOUT.
Ground Pins for TTL output of CLKOUT
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THC63LVD1024_Rev.3.02_E
Pin Description (Continued)
Table 1. Output Control
/PDWN
L
L
H
H
OE
L
H
L
H
Data Outputs
(Rxn)
Hi-Z
All Low
Hi-Z
Data Out
CLKOUT
Hi-Z
Fixed Low
Hi-Z
CLK Out
Absolute Maximum Ratings
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Junction Temperature
Storage Temperature Range
Reflow Peak Temperature / Time
Maximum Power Dissipation @+25
°C
-0.3V ~ +4.0V
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-30mA ~ 30mA
+125
°C
-55
°C
~ +125
°C
+260
°C
/ 10sec.
4.4W
Recommended Operating Conditions
Parameter
All Supply Voltage
Operating Ambient Temperature
MODE<1:0>=LL
Dual-in/Dual-out
Ta
≦
70
°C
(Ta
≦
85
°C
)*
Single Edge Output
CLK
Frequency
MODE<1:0>=LH
Dual-in/Single-out
(MODE2=L)
Double Edge Output
(MODE2=H)
MODE<1:0>=HL
Single-in/Dual-out
MODE<1:0>=HH
Single-in/Single-out
LVDS Input
Min.
3.0
-40
8
Typ
3.3
-
-
Max
3.6
85
135
(80)*
135
(80)*
75
150
75
75
135
67.5
135
135
Unit
V
°C
MHz
Output
LVDS Input
Output
LVDS Input
Output
LVDS Input
Output
LVDS Input
Output
8
20
40
20
20
8
4
8
8
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
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