THCV235_THCV236_Rev.3.30_E
THCV235 and THCV236
SerDes transmitter and receiver with bi-directional transceiver
General Description
The THCV235 and THCV236 are designed to
support video data transmission between the host and
display.
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.
Features
Color depth selectable:24/32bit
RGB
YCbCr422
color space conversion
function
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
Low speed data bridge function
QFN64(9mm x 9mm) with exposed pad ground
V-by-One
®
HS standard version1.4 compliant
EU RoHS compliant
Block Diagram
THCV235
LVCMOS input
Formatter
RGB to YCbCr
D31-D0
HSYNC
VSYNC
DE
CLKIN
Serializer
TXP
TXN
RXP
RXN
THCV236
Deserializer
LVCMOS output
Formatter
YCbCr to RGB
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
Controls
OSC
LDO
TCMP
TCMN
RCMP
RCMN
CDR
PLL
Controls
OSC
Settings
2-wire I/F
SDA/SCL
CAPOUT
CAPINA
CAPINP
LDO
CAPOUT
CAPINA
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THCV235_THCV236_Rev.3.30_E
Contents Page
General Description
.............................................................................................................................................. 1
Features
.................................................................................................................................................................. 1
Block Diagram
....................................................................................................................................................... 1
Pin Configuration
.................................................................................................................................................. 4
Pin Description
...................................................................................................................................................... 5
Functional Overview
........................................................................................................................................... 13
Functional Description
........................................................................................................................................ 13
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
............................................ 13
Power Down (PDN1, PDN0)
........................................................................................................................... 13
Main-Link Mode Setting
................................................................................................................................. 14
V-by-One
®
HS Mode (MAINMODE=0)
........................................................................................................ 14
Sync Free Mode (MAINMODE=1)
................................................................................................................ 14
Color Space Conversion
.................................................................................................................................. 14
Pre-emphasis and Drive Select Function (THCV235 only)
......................................................................... 14
Permanent Clock Output (THCV236 only)
.................................................................................................. 15
Spread Spectrum Clock Generator (SSCG)
.................................................................................................. 15
Data Enable
...................................................................................................................................................... 17
Hot-Plug Function
........................................................................................................................................... 18
Lock Detect Function
...................................................................................................................................... 18
Field BET Operation
....................................................................................................................................... 20
Data Width and Frequency Range Select Function
..................................................................................... 22
Data Mapping
.................................................................................................................................................. 24
Sub-Link Mode Setting
................................................................................................................................... 26
2-wire serial I/F Mode
..................................................................................................................................... 26
2-wire serial I/F Device ID setting ................................................................................................................ 26
2-wire serial I/F Clock Stretching ................................................................................................................. 27
Read/Write access to Sub-Link Master Register ........................................................................................... 28
Read/Write access to Sub-Link Slave Register ............................................................................................. 29
Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device............ 31
GPIO.............................................................................................................................................................. 35
Interruption .................................................................................................................................................... 38
Low Speed Data Bridge Mode
........................................................................................................................ 39
Register Map
........................................................................................................................................................ 40
Absolute Maximum Ratings
............................................................................................................................... 50
Recommended Operating Conditions
................................................................................................................ 50
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THCV235_THCV236_Rev.3.30_E
Electrical Specification
........................................................................................................................................ 50
AC Timing Diagrams and Test Circuits
............................................................................................................ 56
PCB Layout Guideline regarding VDD and AVDD for THCV236
................................................................. 66
Package
................................................................................................................................................................. 67
Notices and Requests
........................................................................................................................................... 68
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THCV235_THCV236_Rev.3.30_E
Pin Configuration
THCV235 (QFN 64pin)
VSYNC
D29
46
D28
45
D27
44
D26
43
D25
42
D24
41
VDD
40
AVDD
39
D23
38
D22
37
D21
36
D20
35
D19
34
D18
33
D17
48
47
VDD
HSYNC
DE
D30
D31
SSEN/GPIO0
BET/GPIO1
CAPOUT
MAINMODE/TCMP
HFSEL/TCMN
TXP
TXN
CAPINA
CAPINP
LOCKN/MSSEL
HTPDN/SUBMODE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
10
12
13
14
15
16
11
1
48
2
47
3
4
5
6
7
8
9
32
31
30
29
28
27
(TOP VIEW)
65 EXPGND
26
25
24
23
22
21
20
19
18
17
VDD
D16
D15
D14
D13
D12
CLKIN
VDD
D11
D10
D9
D8
D7
D6
D5
D4
THCV236 (QFN 64pin)
VSYNC
D2
46
D3
45
D4
44
D5
43
D6
42
D7
41
VDD
40
AVDD
39
D8
38
D9
37
D10
36
D11
35
D12
34
D13
33
D14
VDD
HSYNC
DE
D1
D0
HTPDN/SUBMODE
LOCKN/MSSEL
CAPOUT
RXN
RXP
CAPINA
MAINMODE/RCMN
HFSEL/RCMP
RXDEFSEL
OE
BET
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
D3
D2
D1
D0
LATEN/SD3/AIN1/GPIO4
CMLDRV/SD2/AIN0/GPIO3
PRE/SD1
COL1/SD0
COL0/INT/GPIO2
RF/BETOUT
TEST2
TEST1
LFSEL
PDN1
PDN0
(TOP VIEW)
65 EXPGND
VDD
D15
D16
D17
D18
D19
CLKOUT
VDD
D20
D21
D22
D23
D24/GPIO3
D25/GPIO4
D26
D27
VDD
D28
D29
D30
D31
LATEN/SD3/AIN1/GPIO0
TTLDRV/SD2/AIN0/GPIO1
OUTSEL/SD1
COL1/SD0
COL0/INT/GPIO2
RF/BETOUT
TEST2
TEST1
LFSEL
PDN1
PDN0
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THCV235_THCV236_Rev.3.30_E
Pin Description
Pin Description for THCV235
Pin Name
TXP
TXN
MAINMODE/
TCMP
59
60
57
Pin No.
Type
CO
CO
I/CB
Description
High-Speed CML Signal Output(Main-Link)
High-Speed CML Signal Output(Main-Link)
MAINMODE : Setting V-by-One
®
HS Mode or Sync Free
Mode when PDN1=0. See page12.
0 : V-by-One
®
HS Mode
1 : Sync Free Mode
TCMP : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HFSEL : High Frequency mode select when PDN1=0.
0 : High Frequency mode Disable
1 : High Frequency mode Enable
TCMN : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HTPDN : Hot Plug Detect Input when PDN1=0.
SUBMODE : Sub-Link Mode Select when PDN1=1.
0: 2-wire serial interface(I/F) Mode(default No Clock
Stretching mode)
1: Low Speed Data Bridge Mode
Forbid the different setting between THCV235 and THCV236.
LOCKN : Lock Detect Input when PDN1=0.
MSSEL : Sub-Link Master/Slave Select when PDN1=1.
0 : Sub-Link Master side(inside 2-wire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-wire serial I/F is master)
Sub-Link Master is connected to HOST MPU.
Forbid the same setting between THCV235 and THCV236.
LATEN : Latch select input under Field BET(Main-Link or
Sub-Link).
0 : NOT Latched result
1 : Latched result
SD3 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD3 is output.
When Sub-Link is Slave (MSSEL=1), SD3 is input.
AIN1 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 26.
GPIO4 : General Purpose Input/Output when SUBMODE=0
and MSSEL=1.
When GPIO4 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO4 is used as push pull output or input, no external
component is required.
HFSEL/TCMN
58
I/CB
HTPDN/
SUBMODE
64
IL
LOCKN/MSSEL
63
IL
LATEN/SD3/AIN1/
GPIO4
11
B
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