THC63LVD1027_Rev.4.00_E
THC63LVD1027
Dual Link LVDS Repeater
General Description
The THC63LVD1027 LVDS(Low Voltage Differential
Signaling) repeater is designed to support pixel data
transmission between Host and Flat Panel Display up to
WUXGA resolution.
THC63LVD1027 receives the dual link LVDS data streams
and transmits the LVDS data through various line rate
conversion modes, Dual Link Input / Dual Link Output,
Single Link Input / Dual Link Output, and Dual Link Input /
Single Link Output.
Features
•
30bits/pixel dual link LVDS Receiver
•
30bits/pixel dual Link LVDS Transmitter
•
Operating Temperature Range : -40ºC~85ºC
•
Wide LVDS input skew margin: ± 480ps at 75MHz
•
Accurate LVDS output timing: ± 250ps at 75MHz
•
Reduced swing LVDS output mode supported to
suppress the system EMI
•
Various line rate conversion modes supported
Dual link input / Dual link output [clkout=1x clkin]
Single link input / Dual link output [clkout=1/2x clkin]
Dual link input / Single link output [clkout=2x clkin]
•
Distribution
(signal duplication)
mode supported
•
Power down mode supported
•
3.3V single voltage power supply
•
No external components required for PLLs
•
64pin TSSOP with Exposed PAD
(0.5mm lead pitch)
Block Diagram
Figure 1. Block Diagram
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THC63LVD1027_Rev.4.00_E
Pin Diagram
Figure 2. Pin Diagram
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Pin Description
Pin Name
RA1+/-
RB1+/-
RC1+/-
RD1+/-
RE1+/-
RCLK1+/-
RA2+/-
RB2+/-
RC2+/-
RD2+/-
RE2+/-
RCLK2+/-
TA1+/-
TB1+/-
TC1+/-
TD1+/-
TE1+/-
TCLK1+/-
TA2+/-
TB2+/-
TC2+/-
TD2+/-
TE2+/-
TCLK2+/-
PD
RS
MODE1
MODE0
Direction
Table 1. Pin Description
Type
Description
LVDS data input for channel A of 1st Link
LVDS data input for channel B of 1st Link
LVDS data input for channel C of 1st Link
LVDS data input for channel D of 1st Link
LVDS data input for channel E of 1st Link
LVDS clock input for 1st Link
LVDS data input for channel A of 2nd Link
LVDS data input for channel B of 2nd Link
LVDS data input for channel C of 2nd Link
LVDS data input for channel D of 2nd Link
LVDS data input for channel E of 2nd Link
LVDS clock input for 2nd Link
In Distribution and Single-in/Dual-out mode,RCLK2+/- must be Hi-Z.
LVDS
(See “Mode selection” below in this page.)
LVDS data output for channel A of 1st Link
LVDS data output for channel B of 1st Link
LVDS data output for channel C of 1st Link
LVDS data output for channel D of 1st Link
LVDS data output for channel E of 1st Link
LVDS clock output for 1st Link
LVDS data output for channel A of 2nd Link
LVDS data output for channel B of 2nd Link
LVDS data output for channel C of 2nd Link
LVDS data output for channel D of 2nd Link
LVDS data output for channel E of 2nd Link
LVDS clock output for 2nd Link
Power Down
H: Normal operation
L: Power down state, all LVDS output signals turn to Hi-Z
Input
Output
LVDS output swing level selection
H: Normal swing
L: Reduced swing
Input
LV-TTL
Mode selection
MODE1
L
L
H
L
H
MODE0
L
L
L
H
H
RCLK2+/-
Clkin
Hi-Z
Hi-Z
Clkin
-
Description
Dual-in/Dual-out mode
Distribution mode
Single-in/Dual-out mode
Dual-in/Single-out mode
Reserved
In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z
.
VDD
GND
CAP
Power
-
3.3V power supply pins
Ground pins (Exposed PAD is also Ground)
Decoupling capacitor pins
These pins should be connected to external decoupling capacitors(Ccap).
Recommended Ccap is 0.1
F + 0.01
F.
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Mode Setting
Table 2. Mode Setting
Input/Output
RCLK2+/-
MODE1
(Input mode)
H: Single
L: Dual
Dual-In/Dual-Out
(Fig.3-1,14-1)
Distribution
(Fig.3-2,14-2)
Single-In/Dual-Out
(Fig.3-3,14-3)
Dual-In/Single-Out
(Fig.3-4,14-4)
Reserved
-
H
H
CLK in
L
H
Hi-Z
H
L
Hi-Z
L
L
CLK in
L
MODE0
(Output mode)
H: Single
L: Dual
L
Signal Flow for Each Setting
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
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THC63LVD1027_Rev.4.00_E
Output Control / Fail Safe
THC63LVD1027 has a function to control output depending on LVDS input condition.
Table 3. Output Control
RCLK2+/-
Output
*
All Hi-Z
*
All Hi-Z
CLK in
Refer to p.4 Mode Setting #
Hi-Z
Refer to p.4 Mode Setting #
PD
RCLK1+/-
L
*
H
Hi-Z
H
CLK in
H
CLK in
*: Don’t care
#:
If a particular input data pair is Hi-Z, the corresponding output data become L according to LVDS DC spec.
For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting Hi-Z state.
Figure 4. Fail Safe Circuit
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