Preliminary
PT5620
100V Half Bridge Gate Driver
DESCRIPTION
The PT5620 is a high-speed 100V single-phase gate
driver for power MOSFET and IGBT devices with
independent high and low side referenced output
channels. Built-in dead time protection prevent
damage to the half-bridge. The UVLO circuits prevent
malfunction when VCC and VBS are lower than the
specified threshold voltage. A novel high-voltage BCD
process and common-mode noise canceling
technique provide stable operation of high-side
drivers under high dV/dt noise conditions while
achieving excellent negative transient voltage
tolerance. An enable pin (EN) is included so that
standby mode may be used to set the chip into a low
quiescent current state to realize long battery lifetime.
FEATURES
Integrated 100V half-bridge high side driver
Built-in dead time protection
Under voltage lockout for VCC and VBS
Low operation voltage 5.5V for VCC and VBS
3.3V and 5V input logic compatible
Enable pin (EN) for low standby current
IO+/IO-: +1.5A/–2.5A at VCC=15V, VBS=15V
Dead time adjustment by RDT pin
Common-mode dV/dt noise cancellation circuit
Tolerant of negative transient voltage
–40ºC to 125ºC operating range
Small footprint package：
MSOP10L、
DFN8(3X3)、
DFN10(3X3)
APPLICATIONS
Wireless charging
Half bridge/full bridge converters
BLOCK DIAGRAM
VCC
VCC
VB
UVLO
IN
100KΩ
Input Filter
Pulse
Generator
High Voltage
Level Shifter
R
S
R
Q
Driver
HO
RDT
Dead Time
Floating High-side Control
VCC
Delay
Driver
LO
VS
EN
525KΩ
Input Filter
UVLO
Single Phase
SGND
PGND
PGND
COM
Tel: 886-2-66296288
‧
Fax: 886-2-29174598
‧
http://www.princeton.com.tw
‧
2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan
PT5620
TYPICAL APPLICATION CIRCUIT
PRE 1.0
2
October 2018
PT5620
ORDER INFORMATION
Valid Part No.
PT5620
PT5620
PT5620
Package Type
10 Pins, MSOP
10 Pins, DFN
8 Pins, DFN
Top Code
PT5620
5620
PT5620
PIN CONFIGURATION
1 VCC
2 VB
3
4
HO
VS
PT5620
MSOP10
LO
10
1 VCC
2 VB
3
4
HO
VS
PT5620
DFN10
LO
10
1
2
COM 9
IN
EN
8
7
COM 9
IN
EN
8
VB
HO
VS
LO
8
3
PT 5620
DFN8
COM
7
IN
EN
6
7
4 VCC
5
5 NC
RDT 6
5 NC
RDT 6
PIN DESCRIPTION
Pin Name
Description
MSOP-10
Pin No.
DFN-10
DFN-8
VCC
VB
HO
VS
NC
RDT
EN
IN
COM
LO
Logic and low-side gate drivers power supply voltage
High-side driver floating supply
High-side driver output
High-side driver floating supply offset voltage
Not connected
Connect the resistor to adjust dead time
Logic input for enable mode control
Logic input for gate driver input
Logic ground and low-side gate drivers ground
Low-side gate driver output
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
4
1
2
3
-
-
5
6
7
8
PRE 1.0
3
October 2018
PT5620
FUNCTION DESCRIPTION
LOW SIDE POWER SUPPLY: VCC
VCC is the low side supply which provides power to both input logic and low side output power stage. The built-in under-
voltage lockout circuit enables the device to operate at sufficient power when a typical VCC supply voltage higher than
V
CCUV+
=3.88V is present, as shown in FIG. 1. The PT5620 shuts down all gate driver outputs when the VCC supply
voltage is below
V
CCUV-
=3.66 V, shown as FIG. 1. This prevents the external power devices from extremely low gate
voltage levels during on-state which may result in excessive power dissipation.
V
CC
V
CCMAX
18V
VCC Recommended Area
V
CCMIN
5.5V
V
CCUV+
4.2V
V
CCUV-
3.8V
t
IN
LO
FIG. 1 VCC supply UVLO operating area
HIGH SIDE POWER SUPPLY: VBS
VBS is the high side supply voltage. The total high side circuitry may float with respect to COM following the external
high side power device emitter/source voltage. Due to the internal low power consumption, the entire high side circuitry
may be supplied by a bootstrap topology connected to VCC and may be powered with small bootstrap capacitors. The
device operating region as a function of the supply voltage is given in FIG. 2.
V
BS
V
BSMAX
18V
V
BS
Recommended Area
V
BSMIN
5.5V
V
BSUV+
3.8V
V
BSUV-
3.5V
t
IN
HO
FIG. 2 VBS supply UVLO operating area
CONTROL INPUT LOGIC: VIN
The Schmitt trigger threshold of each input is designed low enough to guarantee LSTTL and CMOS compatibility with
3.3V controller outputs. Input Schmitt triggers and advanced noise filtering provide noise rejection of short input
pulses. An internal pull-down resistor of about 10
-biases each input during the VCC supply
start-up state.
PRE 1.0
4
October 2018
PT5620
DEAD TIME PROTECTION
The PT5620 includes an adjustable dead time protection circuit. The amount of dead time delay is set by the resistance
on the RDT pin. The dead time feature inserts a time delay (a minimum dead time) during which both the high- and low-
side power switches are turned off. This is done to ensure that one power switch has fully turned off before the other
power switch is turned on. FIG. 3 illustrates the dead time period and the relationship between the power switch control
signals.
IN
50%
50%
HO
50%
90%
DT
LO
50%
DT
50%
FIG. 3 Dead time protection
STANDBY MODE
IN
EN
HO
DT
DT
disable
ten
ten
DT
disable
DT
DT
LO
FIG. 4
Logic operation
The PT5620 packaged in MSOP10/DFN10 provides an enable pin (EN) to allow the device to work in a low current
dissipation state. The EN pin is compatible with 3.3/5V logic levels. If EN is set to logic LOW, the device is forced into
standby mode and all gate driver outputs are locked into a logic LOW state and only 5A (typ.) is dissipated, as shown
in FIG. 4. If EN goes from logic LOW to logic HIGH and incorporates a delay of 4.6s (typ.), the device may be released
from standby mode and all outputs are enabled. In order to lower the bias current, a sufficiently large resistor (525K)
is tied between EN and COM.
GATE DRIVER (HO, LO)
High side and low side driver outputs are specifically designed for pulse operation and dedicated to driving power devices
such as IGBTs and power MOSFETs. High and low side outputs are state triggered by the rising and falling edges of
the IN pin, as shown in FIG. 4. After releasing from an under-voltage condition of the VBS supply, a new turn-on signal
(edge) is necessary to activate the respective high side output. In contrast, after releasing from an under-voltage
condition of the VCC supply, the low side outputs may directly switch to the state determined by their respective inputs
without the additional constraints required by the high side driver.
PRE 1.0
5
October 2018
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