PT6311B
VFD Driver/Controller IC
DESCRIPTION
PT6311B is a Vacuum Fluorescent Display (VFD)
Controller driven on a 1/8 to 1/16 duty factor housed in
52-pin plastic LQFP Package. Twelve segment output
lines, 8 grid output lines, 8 segment/grid output drive
lines, one display memory, control circuit, key scan
circuit are all incorporated into a single chip to build a
highly reliable peripheral device for a single chip micro
computer. Serial data is fed to PT6311B via a
three-line serial interface.
FEATURES
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CMOS Technology
Low Power Consumption
Key Scanning (12 x 4 matrix)
Multiple Display Modes: (12 segments, 16 digits to
20 segments, 8 digits)
8-Step Dimming Circuitry
LED Ports Provide (5 channels, 20mA max.)
4- Bits General Purpose Input Ports Provided
Serial Interface for Clock, Data Input, Data Output,
Strobe Pins
No External Resistors Needed for Driver Outputs
Available in 52 pins LQFP
APPLICATION
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Microcomputer Peripheral Devices
BLOCK DIAGRAM
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6311B
PIN DESCRIPTION
Pin Name
SW1 to SW4
DOUT
DIN
NC
CLK
STB
K1 to K4
VDD
SG1/KS1 to SG12/KS12
SG20/GR9 to SG19/GR10
SG18/GR11 to SG13/GR16
VEE
GR1 to GR8
LED1 to LED5
GND
OSC
I/O
I
O
I
-
I
I
I
-
O
O
-
O
O
-
I
Description
General Purpose Input Pins
Data Output Pin (N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift
clock (starting from the lower bit).
Data Input Pin
This pin inputs serial data at the rising edge of the shift clock
(starting from the lower bit).
No Connection
Clock Input Pin
This pin reads serial data at the rising edge and outputs data
at the falling edge.
Serial Interface Strobe Pin
The data input after the STB has fallen is processed as a
command. When this in is “HIGH”, CLK is ignored.
Key Data Input Pins
The data inputted to these pins is latched at the end of the
display cycle.
Logic Power Supply
High-Voltage Segment Output Pins
Also acts as the Key Source.
High-Voltage Segment/Grid Output Pins
Pull-Down Level
High-Voltage Grid Output Pins
LED Output Pin
Ground Pin
Oscillator Input Pin
A resistor is connected to this pin to determine the
oscillation frequency.
Pin No.
1 to 4
5
6
7
8
9
10 to 13
14, 33, 45
15 to 26
36 to 35
32 to 27
34
44 to 37
50 to 46
51
52
V1.0
4
October 2009
PT6311B
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
OUTPUT PINS: SGn/GRn
INPUT PINS: DIN, CLK, STB
INPUT PINS: SW1 TO SW4, K1 TO K4
OUTPUT PIN: DOUT
OUTPUT PINS: LED1 TO LED5
V1.0
5
October 2009
FPGA/CPLD
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