PT7313E
Stereo Audio Processor for Car Audio
DESCRIPTION
The PT7313E is an audio processor designed for
versatile application, including 3 stereo input selectors
with adjustable gain, master volume control with low
frequency loudness compensation, individual output
attenuator and tone control. It is a good solution for
the car audio signal processing.
Due to the high reliability requirement from the car
audio business, the PT7313E improves both audio
performance and input surge current capability that
make PT7313E the best
solution for the cost-effective
car audio systems.
FEATURES
•
3 stereo inputs with gain selection, range from 0dB
to +11.25dB in 3.75dB/step
•
Master volume from 0 dB to -78.75dB in
1.25dB/step
•
Speaker attenuator for balance and fader, range
from 0dB to -38.75dB in 1.25dB/step
•
Each channel output can be muted individually.
•
Low frequency loudness compensation
•
Bass and Treble control, range from -14dB to
+14dB in 2dB/step
•
Wide operation range (VDD = 4V to 10V)
APPLICATIONS
•
Car Audio
•
Home Audio System
•
Powered Speaker System
APPLICATION CIRCUIT
PT2313E
22uF
1 REF
SCL 28
SDA 27
DGND 26
LFOUT 25
RFOUT 24
LROUT 23
RROUT 22
BOUT_R 21
BIN_R 20
BOUT_L 19
BIN_L 18
LOUT 17
LIN 16
LIN1 15
100n
100n
100n
100n
2.2uF
5.6K
10uF
10uF
10uF
10uF
Front Right
Front Left
PT7313E
MCU
VDD
2
VDD
3 AGND
4
2.7n
2.7n
5
6
7
TREB_L
TREB_R
RIN
ROUT
Input Surge
P rotection
L
A UDIO 3
R
L
A UDIO 2
R
L
A UDIO 1
R
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2uF
2.2uF
8 LOUD_R
100n
9
RIN3
2.2uF
2.2uF
2.2uF
2.2uF
2.2uF
10 RIN2
11 RIN1
12 LOUD_L
100n
13 LIN3
14 LIN2
Rear Left
5.6K
Rear Right
P ower
A mplifier
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT7313E
BLOCK DIAGRAM
Speaker Attenuator
With Mute
LROUT
RROUT
REF
REF
LFOUT
RFOUT
REF
REF
TREB_L
BIN_L
BOUT_L
TREBLE
TREBLE
TREB_R
BIN_R
BASS
Master
Volume
REF
BASS
BOUT_R
LOUD_L
LOUDNESS
Loud
SW
REF
LOUDNESS
LOUD_R
LIN
LOUT
LIN1
LIN2
LIN3
RIN
Input SW and
GAIN
ROUT
Input SW and
GAIN
RIN1
RIN2
RIN3
REF
VDD
REF
SCL
I2C
DECODER
SDA
DGND
INT
Ref
REF
REF
BIAS
AGND
V1.0
2
February 2010
PT7313E
ORDER INFORMATION
Valid Part Number
PT7313E-S
Package Type
28 Pins, SOP, 300mil
Top Code
PT7313E
PIN CONFIGURATION
REF
VDD
AGND
TREB_L
TREB_R
RIN
ROUT
1
2
3
4
5
6
7
28 SCL
27 SDA
26 DGND
25 LFOUT
24 RFOUT
23 LROUT
LOUD_R 8
RIN3
9
PT7313E
22 RROUT
21 BOUT_R
20 BIN_R
19 BOUT_L
18 BIN_L
17 LOUT
16 LIN
15 LIN1
RIN2 10
RIN1 11
LOUD_L 12
LIN3 13
LIN2 14
V1.0
3
February 2010
PT7313E
PIN DESCRIPTION
Pin Name
REF
VDD
AGND
TREB_L
TREB_R
RIN
ROUT
LOUD_R
RIN3
RIN2
RIN1
LOUD_L
LIN3
LIN2
LIN1
LIN
LOUT
BIN_L
BOUT_L
BIN_R
BOUT_R
RROUT
LROUT
RFOUT
LFOUT
DGND
SDA
SCL
I/O
-
-
-
I
I
I
O
I
I
I
I
I
I
I
I
I
O
I
O
I
O
O
O
O
O
-
I
I
Description
Analog reference voltage (1/2VDD)
Supply input voltage
Analog ground
Left channel input for treble controller
Right channel input for treble controller
Right channel volume controller input
Right channel Input selector output
Right channel loudness input
Right channel input 3
Right channel input 2
Right channel input 1
Left channel loudness input
Left channel input 3
Left channel input 2
Left channel input 1
Left channel volume controller input
Left channel Input selector output
Left channel input for bass controller
Left channel output for bass controller
Right channel input for bass controller
Right channel output for bass controller
Right rear speaker output
Left rear speaker output
Right front speaker output
Left front speaker output
Digital ground
I
2
C data input
I
2
C clock input
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V1.0
4
February 2010
PT7313E
CONTROL BUS SPECIFICATION
BUS INTERFACE
All functions of the PT7313E are controlled by the I
2
C interface, the interface is consisting by SDA and SCL pins. Detail
protocol of the I
2
C bus will discuss on the next section. It should be noted that the bus level pull-up resistors connected to
the PT7313E positive supply voltage may required in some application especially the MCU output high level is no
enough.
DATA VALIDITY
A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW
State of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below.
START AND STOP CONDITIONS
A Start Condition is activated when
1) The SCL is set to HIGH and
2) SDA shifts from HIGH to LOW State.
The Stop Condition is activated when
1) SCL is set to HIGH and
2) SDA shifts from LOW to HIGH State. Please refer to the timing diagram below..
BYTE FORMAT
Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an Acknowledge Bit. The MSB
is first transmitted.
V1.0
5
February 2010
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