MM74C911 4-Digit Expandable Segment Display Controller
October 1987
Revised January 1999
MM74C911
4-Digit Expandable Segment Display Controller
General Description
The MM74C911 display controller is an interface element
with memory that drives a 4-digit, 8-segment LED display.
The MM74C911 allows individual control of any segment in
the 4-digit display. The number of segments per digit can
be expanded without any external components. For exam-
ple, two MM74C911’s can be cascaded to drive a 16-seg-
ment alpha-numeric display.
The display controllers receive data information through 8
data lines a, b…DP, and digit information through 2
address inputs K1 and K2. The input data is written into the
register selected by the address information when CHIP
ENABLE, CE, and WRITE ENABLE, WE, are LOW and is
latched when either CE or WE return HIGH. Data hold time
is not required.
A self-contained internal oscillator sequentially presents
the stored data to high drive (100 mA typ.) 3-STATE output
drivers which directly drive the LED display. The drivers are
active when the control pin labeled SEGMENT OUTPUT
ENABLE, SOE, is LOW and go into 3-STATE when SOE is
HIGH. This feature allows for duty cycle brightness control,
or for disabling the output drive for power conservation.
The digit outputs directly drive the base of the digit transis-
tor when the control pin labeled DIGIT INPUT OUTPUT,
DIO, is LOW. When DIO is HIGH, the digit lines turn into
inputs and the internal scanning multiplexer is disabled.
When any digit line is forced HIGH by an external device,
usually another MM74C911, the data information for that
digit is presented to the output. In this manner, 16-segment
alpha-numeric displays, 24- or 32-segment displays, or an
array of discrete LED's can be controlled by the simple cas-
cading of expandable segment display controllers. All
inputs except digit inputs are TTL compatible and do not
clamp input voltages above V
CC
.
Features
s
Direct segment drive (100 mA typ.) 3-STATE
s
4 registers addressed like RAM
s
Internal oscillator and scanning circuit
s
Direct base drive to digit transistor
s
Segment expandability without external components
s
TTL compatible inputs
s
Power saver mode—5
µW
(typ.)
Ordering Code:
Order Number
MM74C991N
Package Number
N28B
Package Description
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS−010, 0.600” Wide
Connection Diagram
Pin Assignments for DIP
Top View
© 1999 Fairchild Semiconductor Corporation
DS005915.prf
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MM74C911
Truth Tables
Input Control
Digit
CE
Address
K2
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
K1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
Write Digit 1
Latch Digit 1
Write Digit 2
Latch Digit 2
Write Digit 3
Latch Digit 3
Write Digit 4
Latch Digit 4
Disable Writing
WE
Operation
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
1
DIO
SOE
Output Control
Digit Lines
D4 D3 D2 D1
R
R
0
0
0
0
1
0
R
R
0
0
0
1
0
0
R
R
0
0
1
0
0
0
R
R
0
1
0
0
0
0
Refresh Display
Disable Segment Outputs
Digits Are Now Inputs
Display Digit 1
Display Digit 2
Display Digit 3
Display Digit 4
Power Saver Mode
Operation
R
=
Refresh (digit lines sequentially pulsed)
X
=
Don’t Care
Functional Description
The MM74C911 display controller is manufactured on stan-
dard metal gate CMOS technology. A single 5V 74 series
TTL supply can be used for power and should be bypassed
at the V
CC
pin to suppress current transients.
The digit outputs directly drive the base of a grounded
emitter digit transistor without the need of a Darlington con-
figuration. If an MM74C911 is driving a digit transistor and
also supplying digit information to a cascaded MM74C911,
base resistors are needed in the digit transistors to provide
an adequate high level to the digit inputs of the cascaded
MM74C911.
As seen in the Block Diagram, these display controllers
contain four 8-bit registers; any one may be randomly writ-
ten into. In normal operation, the internal multiplexer scans
the registers and refreshes the display. In cascaded opera-
tion, 1 MM74C911 serves as a master refresh device and
cascaded MM74C911’s are slaved to it through digit lines
operating as inputs.
The MM74C911 appears to a microprocessor as memory
and to the user as a self-scan display. Since every seg-
ment is under microprocessor control, great versatility is
obtained.
Low power standby operation occurs with both SOE and
DIO inputs HIGH. This condition forces the MM74C911 to a
quiescent state typically drawing less than 1
µA
of supply
current with a standby supply voltage as low as 3V.
Logic Diagram
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2
MM74C911
Absolute Maximum Ratings
(Note 1)
(Note 2)
Voltage at Any Pin
except Inputs
Voltage at Any Input
except Digits
Operating Temperature
Range, (T
A
)
Storage Temperature Range
Power Dissipation (P
D
)
−40°C
to
+85°C
−65°C
to
+150°C
Refer to P
D(MAX)
vs T
A
Graph
−0.3V
to
+15V
−0.3V
to V
CC
+
0.3V
Operating V
CC
Range
Absolute Maximum V
CC
Lead Temperature
(Soldering, 10 seconds)
3V to 6V
6.5V
260°C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Range”,
they are not meant to imply that the device should be operated at these lim-
its. The table of “Electrical Characteristics” provides conditions for actual
device operation.
Note 2:
All voltage reference to ground.
DC Electrical Characteristics
Min/Max limits apply at
−40°C ≤
T
J
≤ +85°C,
unless otherwise noted
Symbol
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
I
CC
I
CC
Parameter
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Supply Current (Normal)
Supply Current (Power Saver)
V
CC
=
5V, V
IN
=
15V
V
CC
=
5V, V
IN
=
0V
V
CC
=
5V, Outputs Open
V
CC
=
5V, SOE, DIO
=
“1”,
D1, D2, D3, D4
=
“0”
I
OUT
3-STATE Output Current
V
O
=
5V
V
O
=
0V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
I
SH
Logical “1” Input Voltage
Logical “0” Input Voltage
HIGH Level Segment Current
V
CC
=
4.75V
V
CC
=
4.75V
V
CC
=
5V, V
O
=
3.4V
T
J
=
25°C
T
J
=
100°C
I
DH
HIGH Level Digit Current
V
CC
=
5V, V
O
=
3V
T
J
=
25°C
T
J
=
100°C
V
CC
=
5V, V
O
=
1V
T
J
=
25°C
T
J
=
100°C
V
OUT(1)
V
OUT(0)
θ
JA
Logical “1” Output Voltage,
Any Digit
Logical “0” Output Voltage,
Any Output
Thermal Resistance
(Note 3)
100
°C/W
Note 3:
θ
JA
measured in free-air with device soldered into printed circuit board.
Conditions
V
CC
=
5V
Min
3.0
Typ
Max
Units
V
1.5
0.005
−1.0
−0.005
0.50
1
2.5
600
1.0
V
µA
µA
mA
µA
µA
0.03
−10
V
CC
−
2
−0.03
10
V
0.8
V
OUTPUT DRIVE
−60
−40
−10
−7
−15
−10
4.6
0.4
−100
−60
−20
−10
−40
−15
mA
mA
mA
mA
mA
mA
V
V
V
CC
=
5V, I
O
= −360 µA
V
CC
=
5V, I
O
=
360
µA
3
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MM74C911
AC Electrical Characteristics
V
CC
=
5V, t
r
=
t
f
=
20 ns, C
L
=
50 pF
Symbol
t
CW
t
AW
t
WW
t
DW
t
WD
t
WA
t
WC
t
1H
, t
0H
Parameter
Chip Enable to Write Enable Set-Up Time
Address to Write Enable Set-Up Time
Write Enable Width
Data to Write Enable Set-Up Time
Write Enable to Data Hold Time
Write Enable to Address Hold Time
Write Enable to Chip Enable Hold Time
(Note 4)
Conditions
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
Min
35
50
35
50
400
450
390
430
0
0
0
0
55
75
Typ
15
20
15
20
225
250
225
250
−10
−15
−10
−15
30
40
275
325
325
375
500
700
5
10
10
20
525
375
5
30
7.5
50
500
600
600
700
1000
1400
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Hz
Hz
pF
pF
Logical “1”, Logical “0” Levels into 3-STATE R
L
=10k,
C
L
=10
pF
T
J
=
25°C
T
J
=
125°C
t
H1
, t
H0
3-STATE to Logical “1” or
Logical “0” Levels
R
L
=10k,
C
L
=10
pF
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
T
J
=
25°C
T
J
=
125°C
(Note 5)
(Note 5)
t
D1
, t
D0
t
IB
f
MUX
C
IN
C
OUT
Propagation Delay from Digit Input to
Segment Output
Interdigit Blanking Time
Multiplex Scan Frequency
Input Capacitance
3-STATE Output Capacitance
Note 4:
AC Parameters are guaranteed by DC correlated testing.
Note 5:
Capacitance guaranteed by periodic testing.
Switching Time Waveforms
Write Data Waveforms
3-STATE Waveforms
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4
MM74C911
Switching Time Waveforms
Multiplexing Output Waveforms
(Continued)
Read Data Waveforms
Note A:
All other digit lines are at a low level. DIO at a HIGH level.
Typical Performance Characteristics
Segment outputs if shorted to ground will exceed maximum
power dissipation of the device.
V
CE
is the saturation voltage of the digit drive transistor.
Power Dissipation vs
Temperature for
Plastic Packages
Applications
Segment Output Structure
Digit Output Structure
5
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