LNL04R120
Lonten N-channel 40V, 12A, 12mΩ Power MOSFET
Description
These N-Channel enhancement mode power field
effect
transistors
are
using
trench
DMOS
technology. This advanced technology has been
especially tailored to minimize on-state resistance,
provide superior switching performance, and with
stand high energy pulse in the avalanche and
commutation mode. These devices are well suited
for high efficiency fast switching applications.
Product Summary
V
DSS
R
DS(on).max
@ V
GS
=10V
I
D
40V
12mΩ
12A
Pin Configuration
Features
40V,12A,R
DS(ON).max
=12mΩ@V
GS
=10V
Improved dv/dt capability
Fast switching
Green device available
D
SOP-8
G
S
Applications
Motor Drives
UPS
DC-DC Converter
T
A
= 25°C unless otherwise noted
N-Channel MOSFET
Pb
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Continuous drain current ( T
A
=25°C )
Continuous drain current ( T
A
= 100°C )
Pulsed drain current
1)
Gate-Source voltage
Power Dissipation ( T
A
=25°C )
Storage Temperature Range
Operating Junction Temperature Range
Symbol
V
DSS
I
D
I
DM
V
GSS
P
D
T
STG
T
J
Value
40
12
7.6
48
±20
2.1
-55 to +150
-55 to +150
Unit
V
A
A
A
V
W
°C
°C
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJA
Value
59.5
Unit
°C/W
Version 1.1,Jan-2020
1
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Package Marking and Ordering Information
Device
LNL04R120
Device Package
SOP-8
LNL04R120
Marking
LNL04R120
Electrical Characteristics
Parameter
Static characteristics
Drain-source breakdown voltage
Gate threshold voltage
Drain-source leakage current
Gate leakage current, Forward
Gate leakage current, Reverse
Drain-source on-state resistance
Forward transconductance
T
J
= 25°C unless otherwise noted
Symbol
BV
DSS
V
GS(th)
I
DSS
I
GSSF
I
GSSR
R
DS(on)
g
fs
Test Condition
V
GS
=0 V, I
D
=250uA
V
DS
=V
GS
, I
D
=250uA
V
DS
=40 V, V
GS
=0 V, T
J
= 25°C
V
DS
=32 V, V
GS
=0 V, T
J
= 125°C
V
GS
=20 V, V
DS
=0 V
V
GS
=-20 V, V
DS
=0 V
V
GS
=10 V, I
D
=12 A
V
GS
=4.5 V, I
D
=8 A
V
DS
=5 V , I
D
=20A
Min.
40
1.0
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Typ.
---
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9.2
11.8
35
Max.
---
2.0
1
10
100
-100
12
16
---
Unit
V
V
μA
μA
nA
nA
mΩ
mΩ
S
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate resistance
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
R
g
V
GS
=0V, V
DS
=0V, F=1MHz
V
DD
= 20V,V
GS
=10V, I
D
=12 A
V
DS
= 20 V, V
GS
= 0 V,
F = 1MHz
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1370
158
125
14.5
19.2
61
27
3.5
---
---
---
---
---
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Ω
ns
pF
Gate charge characteristics
Gate to source charge
Gate to drain charge
Gate charge total
Q
gs
Q
gd
Q
g
V
DS
=20V, I
D
=12A,
V
GS
= 10V
---
---
---
7.1
2.9
27.5
---
---
---
nC
Drain-Source diode characteristics and Maximum Ratings
Continuous Source Current
Pulsed Source Current
3)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
I
S
I
SM
V
SD
t
rr
Q
rr
V
GS
=0V, I
S
=10A, T
J
=25℃
I
S
=12A,di/dt=100A/us, T
J
=25℃
---
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---
---
---
---
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21
7.8
12
48
1.2
---
---
A
A
V
ns
nC
Notes:
1: Repetitive Rating: Pulse width limited by maximum junction temperature.
2: Pulse Test：Pulse Width
≤300μs,
Duty Cycle≤2％.
Version 1.1,Jan-2020
2
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LNL04R120
Electrical Characteristics Diagrams
Figure 1. Typ. Output Characteristics
V
GS
=3.5V, 4V, 5V, 8V,10V
From Bottom to Top
Figure 2. Transfer Characteristics
Common Source
V
DS
=5 V
Pulse test
Common Source
T
A
= 25°C
Pulse test
V
GS
=3 V
125°C
25°C
V
GS
=2.5V
Drain−source voltage V
DS
(V)
Gate−source voltage V
GS
(V)
Figure 3. Capacitance Characteristics
Notes:
f = 1 MHz
V
GS
=0 V
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
Figure 4. Gate Charge Waveform
V
gs
= 10 V
V
ds
= 20 V
I
D
= 12 A
Ciss
Coss
Crss
Drain-Source Voltage V
DS
(V)
Total Gate Charge Q
G
(nC)
Figure 5. Body-Diode Characteristics
Figure 6. Rdson-Drain Current
V
GS
= 4.5V
125°C
25°C
V
GS
= 10V
Version 1.1,Jan-2020
Source-Drain Voltage V
SD
(V)
3
Drain Current I
D
(A)
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LNL04R120
Figure 7. Rdson-Junction Temperature(℃)
V
GS
= 10V
I
D
= 12A
Figure 8. Maximum Safe Operating Area
1ms
10ms
Limited by R
DS(on)
DC
Notes:
T = 25°C
T = 150°C
Single Pulse
j
A
100ms
1s
T -Junction Temperation (
°C
)
J
Drain-Source Voltage V
DS
(V)
Figure 9. Normalized Maximum Transient Thermal Impedance (RthJA)
Pulse Width t (s)
Version 1.1,Jan-2020
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LNL04R120
Test Circuit & Waveform
Figure 8. Gate Charge Test Circuit & Waveform
Figure 9. Resistive Switching Test Circuit & Waveforms
Figure 10. Unclamped Inductive Switching (UIS) Test Circuit & Waveform
Figure 11. Diode Recovery Circuit & Waveform
Version 1.1,Jan-2020
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