Fremont Micro Devices
FT24C02A-Kxx
Two-Wire Serial EEPROM
2K (8-bit wide)
FEATURES
Low voltage and low power operations:
FT24C02A: VCC = 1.8V to 5.5V, Industrial temperature range (-40℃ to 85℃).
FT24C02A-Kxx: With 3 bits device address, the devices are suitable for all application. (For use
of 5 pins package, the device address A2,A1,and A0 bits must be set to zero)
16 bytes page write mode.
Partial page write operation allowed.
Internally organized: 256
×
8 (2K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed programming cycle (5ms maximum).
1 MHz (2.5-5V), 400 kHz (1.8V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
Standard 8-pin DIP/SOP/MSOP/TSSOP/DFN and 5-pin SOT-23/TSOT-23 Pb-free packages.
DESCRIPTION
The FT24C02A is 2048 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly
known as EEPROM. They are organized as 256 words of 8 bits (1 byte) each. The devices are fabricated with
proprietary advanced CMOS process for low power and low voltage applications. These devices are available in
standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, 8-lead DFN and 5-lead SOT-23/TSOT-23
packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V
CC
range (1.8V to 5.5V) devices enables wide spectrum of applications.
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C02A-Kxx-page1
Fremont Micro Devices
FT24C02A-Kxx
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
VCC
GND
NC
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
Power Supply
Ground
No-Connect
Table 1
All these packaging types come in conventional or Pb-free certified.
Figure 1: Package types
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature……………………………………………………………………………..-40℃ to 85℃
Storage temperature…………………………………………………………………………………………-50℃ to 125℃
Input voltage on any pin relative to ground…………………………………………………………..-0.3V to V
CC
+ 0.3V
Maximum voltage…………………………………………………………………………………………………………..8V
ESD protection on all pins…………………………………………………………………………………………...>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. Functional operation of the device at conditions beyond those listed in the specification is not
guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality.
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C02A-Kxx-page2
Fremont Micro Devices
FT24C02A-Kxx
Block Diagram
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
Figure 2: Block Diagram
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to
clock data out of the EEPROM device.
(B) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-
OR with other open-drain output devices.
(C) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to
either VIH or VIL. If left unconnected, they are internally recognized as VIL. However, due to capacitive coupling
that may appear in customer applications, FMD recommends always connecting the address pins to a known
state. When using a pull-up or pull-down resistor, FMD recommends using 10kΩ or less.
(D) WRITE PROTECT (WP)
The FT24C02A devices have a WP pin to protect the whole EEPROM array from programming. Programming
operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C02A-Kxx-page3
Fremont Micro Devices
FT24C02A-Kxx
disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level. If left
unconnected, it is internally recognized as VIL. However, due to capacitive coupling that may appear in customer
applications, FMD recommends always connecting the WP pin to a known state. When using a pull-up or pull-
down resistor, FMD recommends using 10kΩ or less.
MEMORY ORGANIZATION
The FT24C02A devices have 16 pages. Since each page has 16 bytes, random word addressing to FT24C02A
will require 8 bits data word addresses.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock
SCL is at V
IL
. Any SDA signal transition may interpret as either a START or STOP condition as described below.
(B) START CONDITION
With SCL
≥
V
IH
, a SDA transition from high to low is interpreted as a START condition. All valid commands
must begin with a START condition.
(C) STOP CONDITION
With SCL
≥
V
IH
, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write
commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command.
A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-
timed internal programming finish.
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM
acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal
occurs on the 9th serial clock after each word.
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read
mode, or after completing a self-time internal programming operation.
(F) SOFT RESET
After an interruption in protocol power loss or system reset, any two-wire part can be reset by following these
steps:
1. Creat a START condition,
2. Clock eighteen data bits “1”,
3. Creat a start condition as SDA is high.
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C02A-Kxx-page4
Fremont Micro Devices
FT24C02A-Kxx
SCL
SDA
START
Condition
Data
Valid
Data
Transition
STOP
Condition
Figure 3: Timing diagram for START and STOP conditions
START Condition
SCL
Data in
Data out
ACK
Figure 4: Timing diagram for output ACKNOWLEDGE
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C02A-Kxx-page5
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