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VS1053B-L

产品描述MP3芯片
产品类别模拟混合信号IC    视频音频接口芯片   
文件大小736KB,共80页
制造商VLSI
官网地址http://www.vlsi.fi/
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VS1053B-L概述

MP3芯片

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VS1053b preliminary
VS1053
B
VS1053b -
Ogg Vorbis/MP3/AAC/WMA/MIDI
AUDIO CODEC
Features
Description
Decodes
Ogg Vorbis;
VS1053b is a single-chip Ogg Vorbis/MP3/AAC/-
MPEG 1 & 2 audio layer III (CBR +VBR
WMA/MIDI audio decoder and an IMA ADPCM
+ABR); layers I & II optional;
and user-loadable Ogg Vorbis encoder. It contains
MPEG4 / 2 AAC-LC(+PNS),
a high-performance, proprietary low-power DSP
HE-AAC v2 (Level 3)
(SBR + PS);
processor core VS DSP
4
, working data memory,
WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps);
16 KiB instruction RAM and 0.5+ KiB data RAM
WAV (PCM + IMA ADPCM);
for user applications running simultaneously with
General MIDI 1 / SP-MIDI format 0 files
any built-in decoder, serial control and input data
Encodes Ogg Vorbis with software plu-
interfaces, upto 8 general purpose I/O pins, an
gin
(available Q4/2007)
UART, as well as a high-quality variable-sample-
rate stereo ADC (mic, line, line + mic or 2×line)
Encodes
IMA ADPCM
from mic/line (stereo)
and stereo DAC, followed by an earphone ampli-
Streaming support for MP3 and WAV
fier and a common voltage buffer.
EarSpeaker Spatial Processing
Bass and treble controls
VS1053b receives its input bitstream through a
Operates with a single 12..13 MHz clock
serial input bus, which it listens to as a system
Can also be used with a 24..26 MHz clock
slave. The input stream is decoded and passed
through a digital volume control to an 18-bit over-
Internal PLL clock multiplier
sampling, multi-bit, sigma-delta DAC. The decod-
Low-power operation
ing is controlled via a serial control bus. In addi-
High-quality on-chip stereo DAC with no
tion to the basic decoding, it is possible to add
phase error between channels
application specific features, like DSP effects, to
Zero-cross detection for smooth volume
the user RAM memory.
change
Stereo earphone driver capable of driving a
Optional factory-programmable unique chip ID pro-
30
load
vides basis for digital rights management or unit
Quiet power-on and power-off
identification features.
I2S interface for external DAC
I2S
Separate voltages for analog, digital, I/O
audio
VS1053
L
Stereo Ear−
Stereo
Stereo
On-chip RAM for user code and data
differential1
MUX
MIC AMP
mic / line
phone Driver
ADC
DAC
R
line 2
output
Serial control and data interfaces
8
GPIO
GPIO
Can be used as a slave co-processor
X ROM
DREQ
SPI flash boot for special applications
SO
Serial
SI
X RAM
Data/
UART for debugging purposes
4
SCLK
Control
VSDSP
Interface
New functions may be added with software
XCS
XDCS
Y ROM
and upto 8 GPIO pins
RX
Lead-free RoHS-compliant package (Green)
TX
UART
Y RAM
Clock
multiplier
Instruction
RAM
Instruction
ROM
Version 0.5,
2007-12-03
1

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VS1053B-L
描述 MP3芯片

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