For air-conditioner fan motor
3-Phase Brushless Fan Motor
Controller
BD62011AFS
General Description
This controller synthesizes the optimal driving signal
from hall sensor signals, and outputs the synthesized
signal to control the external level shifter and power
transistor. The replacement is also easy because of its
pin compatibility with BD62012AFS and BD62014AFS.
This controller provides optimum motor drive for a wide
variety of applications, and enables motor unit
standardization.
Features
180° sinusoidal commutation logic
PWM control (Upper and lower arm switching)
Phase control supported from 0° to +40° at 1°
intervals
Rotational direction switch
FG signal output with pulse number switch (4 or 12)
VREG output (5V/30mA)
Protection circuits provided: OCP, UVLO, TSD, MLP
and the external fault input (FIB)
Applications
Air conditioners; air cleaners; water pumps;
dishwashers; washing machines
General OA equipment
Key Specifications
Supply voltage range:
Duty control voltage range:
Phase control range:
Operating temperature:
Junction Temperature:
Power dissipation:
10V to 18V
2.1V to 5.4V
0° to 40°
-40°C to 110°C
+150°C
1.0W
Package
SSOP-A24
W (Typ.) x D (Typ.) x H (Max.)
10.00 mm x 7.80 mm x 2.10 mm
SSOP-A24
Typical Application Circuit
VREG
FG
VSP
R1
C1
Q1
R8
R9
C13
DTR
BD62011AFS
BD62011FS
C14
C7
C2~C4
C8
HW
HV
HU
R2
VREG
C11
C5
C9
C10
R5
R4
R3
C6
D1
R7
C12
M
VCC
GND
BM6202FS
R6
VDC
Figure 1. Application circuit example - BD62011AFS & BM6202FS
Product
structure : Silicon monolithic integrated circuit
.
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© 2015 ROHM Co., Ltd. All rights reserved.
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product is not designed protection against radioactive rays
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BD62011AFS
Block Diagram and Pin Configuration
VCC
VREG
22
VREG
VDC
UH
UL
DRIVER
VH
VL
WH
WL
Datasheet
3
VREG
TSD
VREG
UVLO
HUP
HU
HUN
HVP
HV
HVN
HWP
HW
HWN
21
20
19
18
17
16
LOGIC
DRIVER
10
9
8
7
6
5
M
FG 14
6
3
3
PWM BUS
FILTER
4
RCL
PC
23
+
A/D
SINUSOIDAL
WAVE GENE.
PCT
24
V/I
13
FGS
12
CCW
FIB
GND
RT
VCC
RCL
WL
WH
VL
VH
UL
UH
FIB
CCW
PCT
PC
VREG
HUP
HUN
HVP
HVN
HWP
HWN
VSP
FG
FGS
TEST
VSP
15
OSC
11
FAULT
2
RT
GND
1
Figure 2. Block diagram
Figure 3. Pin configuration
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Name
GND
RT
VCC
RCL
WL
WH
VL
VH
UL
UH
FIB
CCW
Function
Signal ground
Carrier frequency setting pin
Power supply
Over current sense pin
Low side driver output phase W
High side driver output phase W
Low side driver output phase V
High side driver output phase V
Low side driver output phase U
High side driver output phase U
External fault input (Low active)
Direction switch (H:CCW)
Pin
24
23
22
21
20
19
18
17
16
15
14
13
Name
PCT
PC
VREG
HUP
HUN
HVP
HVN
HWP
HWN
VSP
FG
FGS
Function
VSP offset voltage output pin
Phase control input pin
Regulator output
Hall input pin phase U+
Hall input pin phase U-
Hall input pin phase V+
Hall input pin phase V-
Hall input pin phase W+
Hall input pin phase W-
Duty control voltage input pin
FG signal output
FG pulse # switch (H:12, L:4)
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BD62011AFS
Functional Descriptions
Datasheet
1) Commutation logic
When the hall cycle is about 5-Hz or less (e.g. when the motor starts up), the commutation mode is 120° square wave
drive with upper and lower switching (no lead angle). The controller monitors the hall cycle, and switches to 180°
sinusoidal commutation drive when the hall cycle reaches or exceeds about 5-Hz over four consecutive cycles. Refer to
the timing charts in figures 7 and 8.
Table 1. 120° commutation (Six-state) truth table (CW)
HU
H
H
H
L
L
L
HV
L
L
H
H
H
L
HW
H
L
L
L
H
H
UH
L
L
L
PWM
PWM
L
VH
PWM
L
L
L
L
PWM
WH
L
PWM
PWM
L
L
L
UL
H
H
L
--------------------
VL
--------------------
WL
L
--------------------
PWM
L
H
H
L
PWM
PWM
L
H
H
--------------------
PWM
PWM
L
--------------------
--------------------
PWM
2) Duty control
The switching duty can be controlled by forcing DC voltage with value from V
SPMIN
to V
SPMAX
to the VSP pin. When the
VSP voltage is higher than V
SPTST
, the controller forces PC pin voltage to ground (Testing mode, maximum duty and no
lead angle). The VSP pin is pulled down internally by a 200 kΩ resistor. Therefore, note the impedance when setting the
VSP voltage with a resistance voltage divider.
3) Carrier frequency setting
The carrier frequency setting can be freely adjusted by connecting an external
resistor between the RT pin and ground. The RT pin is biased to a constant
voltage, which determines the charge current to the internal capacitor. Carrier
frequencies can be set within a range from about 16 kHz to 50 kHz. Refer to
the formula to the right.
4) FG signal output
The number of FG output pulses can be switched in accordance with the number
of poles and the rotational speed of the motor. The FG signal is output from the FG
pin. The 12-pulse signal is generated from the three hall signals (exclusive NOR),
and the 4-pulse signal is the same as hall U signal. It is recommended to pull up
FGS pin to VREG voltage when malfunctioning because of the noise.
5) Direction of motor rotation setting
The direction of rotation may be switched by the CCW pin. When CCW pin is “H”
or open, the motor rotates at CCW direction. When the real direction is different
from the setting, the commutation mode is 120° square wave drive (no lead angle).
It is recommended to pull up CCW pin to VREG voltage when malfunctioning
because of the noise.
F
OSC
[kHz]
=
400
R
T
[kΩ]
FGS
H
L
No. of pulse
12
4
CCW
H
L
Direction
CCW
CW
6) Hall signal comparator
The hall comparator provides voltage hysteresis to prevent noise malfunctions. The bias current to the hall elements
should be set to the input voltage amplitude from the element, at a value higher than the minimum input voltage, V
HALLMIN
.
We recommend connecting a ceramic capacitor with value from 100 pF to 0.01 µF, between the differential input pins of
the hall comparator. Note that the bias to hall elements must be set within the common mode input voltage range
V
HALLCM
.
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BD62011AFS
Datasheet
7) Output duty pulse width limiter
Pulse width duty is controlled during PWM switching in order to ensure the operation of external power transistor. The
controller doesn’t output pulse of less than T
MIN
(0.8µs minimum). Dead time is forcibly provided to prevent external
power transistors to turn-on simultaneously in upper and lower side in driver output (for example, UH and UL) of each
arm. This will not overlap the minimum time T
DT
(1.6µs minimum). Because of this, the maximum duty of 120° square
wave drive at start up is 90% (typical).
8) Phase control setting
The driving signal phase can be advanced to the hall signal for phase control. The lead angle is set by forcing DC
voltage to the PC pin. The input voltage is converted digitally by a 6-bit A/D converter, in which internal VREG voltage is
assumed to be full-scale, and the converted data is processed by a logic circuit. The lead angle can be set from 0° to
+40° at 1° intervals, and updated fourth hall cycle of phase W falling edge. Phase control function only operates at
sinusoidal commutation mode. However, the controller forces PC pin voltage to ground (no lead angle) during testing
mode. The VSP offset voltage (Figure 29) is buffered to PCT pin, to connect an external resistor between PCT pin and
ground. The internal bias current is determined by PCT voltage and the resistor value - V
PCT
/ R
PCT
-, and mixed to PC
pin. As a result, the lead angle setting is followed with the duty control voltage, and the performance of the motor can be
improved. Please select the R
PCT
value from 50 kΩ to 200 kΩ in the range on the basis of 100 kΩ, because the PCT pin
current capability is a 100 µA or less.
V
SPMIN
L.A.
VSP
V
PCT
= VSP-V
SPMIN
V
PCT
R
PCT
PCT
L.A.
PC
R
PCL
R
PCT
ADC
VSP
Figure 4. Phase control setting example 1
VREG
VSP
V
SPMIN
L.A.
ADC
V
PCT
= VSP-V
SPMIN
V
PCT
R
PCT
PC
PCT
L.A.
R
PCH
R
PCL
R
PCT
VSP
Figure 5. Phase control setting example 2
9) Overcurrent protection (OCP) circuit
The over current protection circuit can be activated by connecting a low value resistor for current detection between the
external output stage ground and the controller IC ground. When the RCL pin voltage reaches or surpasses the threshold
value, the controller forces all the upper switching arm inputs low (UH, VH, WH = L, L, L), thus initiating the overcurrent
protection operation. When the RCL pin voltage swings below the ground, it is recommended to insert a resistor - 1.5 kΩ
or more - between RCL pin and current detection resistor to prevent malfunction. Since this protection circuit is not a
latch type, it returns to normal operation - synchronizing with the carrier frequency - once the RCL pin voltage falls below
the threshold voltage. A filter is built into the overcurrent detection circuit to prevent malfunctions, and does not activate
when a short pulse of less than T
RCL
is present at the input.
10) Under voltage lock out (UVLO) circuit
To secure the lowest power supply voltage necessary to operate the controller, and to prevent under voltage
malfunctions, an UVLO circuit is built into this controller. When the power supply voltage falls to V
UVL
or below, the
controller forces all driver outputs low. When the voltage rises to V
UVH
or above, the UVLO circuit ends the lock out
operation and returns the chip to normal operation.
The voltage monitor circuit (4.0V nominal) is built-in for the VREG voltage. Therefore, the UVLO circuit does not release
operation when the VREG voltage rising is delayed behind the VCC voltage rising even if VCC voltage becomes V
UVH
or
more.
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BD62011AFS
Datasheet
11) Thermal shutdown (TSD) circuit
The TSD circuit operates when the junction temperature of the controller exceeds the preset temperature (175°C
nominal). At this time, the controller forces all driver outputs low. Since thermal hysteresis is provided in the TSD circuit,
the chip returns to normal operation when the junction temperature falls below the preset temperature (150°C nominal).
The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or
guarantee its operation in the presence of extreme heat. Do not continue to use the IC after the TSD circuit is activated,
and do not use the IC in an environment where activation of the circuit is assumed.
12) Motor lock protection (MLP) circuit
When the controller detects the motor locking during fixed time of 4 seconds nominal when each edge of the hall signal
doesn't input either, the controller forces all driver outputs low under a fixed time 20 seconds nominal, and self-returns to
normal operation. This circuit is enabled if the voltage force to VSP is over the duty minimum voltage V
SPMIN
, and note
that the motor cannot start up when the controller doesn’t detect the motor rotation by the minimum duty control.
13) External fault signal input pin (FIB pin, low active)
The FIB pin can force all controller driver outputs low at any time. The FIB pin is pulled up to VREG internally by a 100
kΩ resistor. Therefore, an open drain output can be connected directly. It is recommended to pull up FIB pin to VREG
voltage when this function is not used or malfunctioning because of the noise.
14) Hall signal wrong input detection
Hall element abnormalities may cause incorrect inputs that vary from the normal logic. When all hall input signals go high
or low, the hall signal wrong input detection circuit forces all driver outputs low. And when the controller detects the
abnormal hall signals continuously for four times or more motor rotation, the controller forces all driver outputs low and
latches the state. It is released if the duty control voltage VSP is forced to ground level once.
15) Internal voltage regulator
The internal voltage regulator VREG is output for the bias of the hall
element and the phase control setting. However, when using the VREG
function, be aware of the I
OMAX
value. If a capacitor is connected to the
ground in order to stabilize output, a value of 1 µF or more should be used.
In this case, be sure to confirm that there is no oscillation in the output.
VCC
VREG
R1
HUP
HU
HUN
HVP
HV
HVN
HWP
HW
HWN
Controller IC
Figure 6. VREG output pin application example
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