RTL8306E-CG
SINGLE-CHIP 6-PORT 10/100MBPS
ETHERNET SWITCH CONTROLLER WITH
DUAL MII/RMII INTERFACES
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.1
03 November 2010
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8306E
Datasheet
COPYRIGHT
©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2010/08/05
2010/11/03
Summary
First release.
Revised Table 3 Mode Configuration Pin Definitions, page 9.
Revised Table 29 Spd and Bi-Color Link/Act Truth Table when the RTL8306E
Controls LED, page 77.
Revised Table 78 MII/TMII/RMII/SMI Timing, page 110.
Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller
with Dual MII/RMII Interfaces
ii
Track ID: JATR-2265-11 Rev. 1.1
RTL8306E
Datasheet
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ..............................................................................................................................................1
FEATURES .........................................................................................................................................................................3
SYSTEM APPLICATIONS...............................................................................................................................................4
BLOCK DIAGRAM ...........................................................................................................................................................5
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
5.2.
5.3.
6.
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
P
IN
A
SSIGNMENTS
D
IAGRAM
.......................................................................................................................................6
P
ACKAGE
I
DENTIFICATION
...........................................................................................................................................6
P
IN
A
SSIGNMENTS
T
ABLE
............................................................................................................................................7
M
EDIA
C
ONNECTION
P
INS
...........................................................................................................................................9
M
ODE
C
ONFIGURATION
P
INS
.......................................................................................................................................9
P
ORT
4 MAC C
IRCUIT
I
NTERFACE
P
INS
......................................................................................................................13
P
ORT
4 PHY C
IRCUIT
I
NTERFACE
P
INS
......................................................................................................................16
M
ISCELLANEOUS
P
INS
...............................................................................................................................................20
P
ORT
LED P
INS
.........................................................................................................................................................21
S
ERIAL
EEPROM
AND
SMI P
INS
..............................................................................................................................23
S
TRAPPING
P
INS
.........................................................................................................................................................24
P
ORT
S
TATUS
S
TRAPPING
P
INS
..................................................................................................................................26
P
OWER
P
INS
...............................................................................................................................................................27
PIN DESCRIPTIONS.........................................................................................................................................................9
BASIC FUNCTIONAL DESCRIPTION........................................................................................................................28
7.1.
S
WITCH
C
ORE
F
UNCTION
O
VERVIEW
.........................................................................................................................28
7.1.1. Dual MII/RMII .....................................................................................................................................................28
7.1.1.1
7.1.1.2
7.1.1.3
Description....................................................................................................................................................................28
Dual MII/RMII Mode Configuration ............................................................................................................................29
Port4 (5th Port) and Port5 (6th MAC) Status Configuration.........................................................................................30
7.1.2.
7.1.3.
Port0, 1, 2, 3 Status Configuration.......................................................................................................................30
Flow Control ........................................................................................................................................................31
IEEE 802.3x Full Duplex Flow Control........................................................................................................................31
Force Mode Full Duplex Flow Control.........................................................................................................................31
Half Duplex Back Pressure ...........................................................................................................................................31
NWay Mode..................................................................................................................................................................31
Force Mode...................................................................................................................................................................32
7.1.3.1
7.1.3.2
7.1.3.3
7.1.3.4
7.1.3.5
7.1.4. Address Search, Learning, and Aging ..................................................................................................................32
7.1.5. Half Duplex Operation .........................................................................................................................................32
7.1.6. InterFrame Gap....................................................................................................................................................33
7.1.7. Illegal Frame........................................................................................................................................................33
7.2.
P
HYSICAL
L
AYER
F
UNCTIONAL
O
VERVIEW
...............................................................................................................33
7.2.1. Auto-Negotiation for UTP ....................................................................................................................................33
7.2.2. 10Base-T Transmit Function ................................................................................................................................33
7.2.3. 10Base-T Receive Function ..................................................................................................................................33
7.2.4. Link Monitor.........................................................................................................................................................33
7.2.5. 100Base-TX Transmit Function............................................................................................................................33
7.2.6. 100Base-TX Receive Function..............................................................................................................................34
7.2.7. Power-Down Mode...............................................................................................................................................34
7.2.8. Crossover Detection and Auto Correction ...........................................................................................................34
7.2.9. Polarity Detection and Correction .......................................................................................................................34
7.3.
G
ENERAL
F
UNCTION
O
VERVIEW
................................................................................................................................35
7.3.1. Power-on Sequence ..............................................................................................................................................35
Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller
with Dual MII/RMII Interfaces
iii
Track ID: JATR-2265-11 Rev. 1.1
RTL8306E
Datasheet
7.3.2.
7.3.3.
7.3.4.
7.3.5.
7.3.6.
7.3.7.
7.3.8.
7.3.9.
7.3.10.
7.3.11.
7.3.12.
8.
Reset .....................................................................................................................................................................36
Setup and Configuration.......................................................................................................................................37
Serial EEPROM Example: 24LC01/02/04 ...........................................................................................................38
24LC02/04 Device Operation .......................................................................................................................................38
EEPROM Size Selection...............................................................................................................................................40
7.3.4.1
7.3.4.2
SMI .......................................................................................................................................................................40
Head-Of-Line Blocking ........................................................................................................................................41
Filtering/Forwarding Reserved Control Frame ...................................................................................................41
Loop Detection .....................................................................................................................................................41
MAC Local Loopback Return to External ............................................................................................................44
Reg.0.14 PHY Digital Loopback Return to Internal........................................................................................45
1.8V Power Generation ...................................................................................................................................46
Crystal/Oscillator ............................................................................................................................................46
ADVANCED FUNCTION DESCRIPTION...................................................................................................................47
8.1.
ACL F
UNCTION
.........................................................................................................................................................47
8.2.
MAC L
IMIT
...............................................................................................................................................................48
8.3.
P
ORT
I
SOLATION
........................................................................................................................................................48
8.4.
VLAN F
UNCTION
......................................................................................................................................................48
8.4.1. Description ...........................................................................................................................................................48
8.4.2. Port-Based VLAN .................................................................................................................................................50
8.4.3. IEEE 802.1Q Tagged-VID Based VLAN ..............................................................................................................52
8.4.4. Insert/Remove/Replace Tag..................................................................................................................................53
8.4.5. VLAN Translation.................................................................................................................................................53
8.4.6. QinQ Function......................................................................................................................................................53
8.4.7. Ingress and Egress Rules......................................................................................................................................53
8.5.
IEEE 802.1
P
R
EMARKING
F
UNCTION
.........................................................................................................................54
8.6.
Q
O
S F
UNCTION
..........................................................................................................................................................55
8.6.1. Bandwidth Control ...............................................................................................................................................55
8.6.1.1
8.6.1.2
Introduction...................................................................................................................................................................55
Input (RX) Bandwidth Control .....................................................................................................................................56
Queue Number Selection ..............................................................................................................................................57
Port-Based Priority Assignment....................................................................................................................................57
IEEE 802.1p/Q-Based Priority Assignment..................................................................................................................57
DSCP-Based Priority Assignment ................................................................................................................................57
12-Bit VLAN ID Priority..............................................................................................................................................57
IP Address-Based Priority.............................................................................................................................................57
IGMP/MLD-Based Priority ..........................................................................................................................................58
CPU Tag-Based Priority ...............................................................................................................................................58
ACL-Based Priority Assignment ..................................................................................................................................58
Packet Priority Selection...............................................................................................................................................58
Priority Controlled By Strapping Pin ............................................................................................................................59
8.6.2.
Priority Assignment ..............................................................................................................................................56
8.6.2.1
8.6.2.2
8.6.2.3
8.6.2.4
8.6.2.5
8.6.2.6
8.6.2.7
8.6.2.8
8.6.2.9
8.6.2.10
8.6.2.11
8.7.
L
OOKUP
T
ABLE
F
UNCTION
........................................................................................................................................60
8.7.1. Function Description............................................................................................................................................60
8.7.2. Address Search, Learning, and Aging ..................................................................................................................60
8.7.3. Lookup and CAM Table Definition ......................................................................................................................62
8.7.3.1
8.7.3.2
Lookup Table Access....................................................................................................................................................62
Least Recently Used (LRU) Function Description .......................................................................................................62
8.8.
MIBS F
UNCTION
........................................................................................................................................................63
8.8.1. MIB Counter Description .....................................................................................................................................63
8.8.2. MIB Counter Enable/Clear ..................................................................................................................................63
8.8.3. MIB Counter Timeout...........................................................................................................................................64
8.9.
S
TORM
F
ILTER
F
UNCTION
..........................................................................................................................................64
8.9.1. Definition..............................................................................................................................................................64
8.9.2. Type 1 Storm Filter...............................................................................................................................................64
Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller
with Dual MII/RMII Interfaces
iv
Track ID: JATR-2265-11 Rev. 1.1
RTL8306E
Datasheet
8.9.3. Type 2 Storm Filter...............................................................................................................................................65
8.10.
CPU I
NTERRUPT
F
UNCTION
.......................................................................................................................................66
8.11.
IGMP & MLD S
NOOPING
F
UNCTION
.........................................................................................................................67
8.12.
CPU T
AG
F
UNCTION
..................................................................................................................................................68
8.13.
IEEE 802.1
X
F
UNCTION
.............................................................................................................................................70
8.13.1.
Port-Based Access Control..............................................................................................................................70
8.13.2.
MAC-Based Access Control.............................................................................................................................70
8.14.
IEEE 802.1D F
UNCTION
............................................................................................................................................71
8.15.
I
NPUT
& O
UTPUT
D
ROP
F
UNCTION
............................................................................................................................73
8.16.
P
ORT
M
IRRORING
......................................................................................................................................................74
8.17.
LED F
UNCTION
..........................................................................................................................................................75
8.17.1.
RTL8306E Controlling LED............................................................................................................................77
8.17.2.
CPU Controlling LED .....................................................................................................................................77
8.18.
G
REEN
E
THERNET
......................................................................................................................................................78
8.19.
E
NERGY
-E
FFICIENT
E
THERNET
(EEE) .......................................................................................................................78
8.20.
W
AKE
-
ON
-LAN (WOL) ............................................................................................................................................79
8.21.
CPU P
ORT
T
RAFFIC
R
ATE
M
ONITOR
.........................................................................................................................79
8.22.
C
ABLE
D
IAGNOSIS
.....................................................................................................................................................79
9.
REGISTER DESCRIPTIONS.........................................................................................................................................80
9.1.
R
EGISTER
L
IST
...........................................................................................................................................................80
9.2.
PHY 0 R
EGISTERS
......................................................................................................................................................82
9.2.1. PHY 0 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................82
9.2.2. PHY 0 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................83
9.2.3. PHY 0 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................83
9.2.4. PHY 0 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................84
9.2.5. PHY 0 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................84
9.2.6. PHY 0 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................85
9.2.7. PHY 0 Register 16 (Page 0, 1, 2, 3): Global Control 0........................................................................................86
9.2.8. PHY 0 Register 18 (Page 0, 1): Global Control 2................................................................................................87
9.2.9. PHY 0 Register 19 (Page 0, 1): Global Control 3................................................................................................87
9.2.10.
PHY 0 Register 22 (Page 0, 1): Port 0 Control Register 0..............................................................................88
9.2.11.
PHY 0 Register 24 (Page 0, 1): Port 0 Control Register 1..............................................................................89
9.3.
PHY 1 R
EGISTERS
......................................................................................................................................................89
9.3.1. PHY 1 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................89
9.3.2. PHY 1 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................89
9.3.3. PHY 1 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................89
9.3.4. PHY 1 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................89
9.3.5. PHY 1 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................89
9.3.6. PHY 1 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................90
9.3.7. PHY 1 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................90
9.3.8. PHY 1 Register 24 (Page 0, 1): Port 1 Control Register 1...................................................................................90
9.4.
PHY 2 R
EGISTERS
......................................................................................................................................................91
9.4.1. PHY 2 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................91
9.4.2. PHY 2 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................91
9.4.3. PHY 2 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................91
9.4.4. PHY 2 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................91
9.4.5. PHY 2 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................91
9.4.6. PHY 2 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................91
9.4.7. PHY 2 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................91
9.4.8. PHY 2 Register 23 (Page 0, 1): Global Option Register 1...................................................................................91
9.4.9. PHY 2 Register 24 (Page 0, 1): Port 2 Control Register 2...................................................................................92
9.5.
PHY 3 R
EGISTERS
......................................................................................................................................................92
9.5.1. PHY 3 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................92
9.5.2. PHY 3 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................92
Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller
with Dual MII/RMII Interfaces
v
Track ID: JATR-2265-11 Rev. 1.1
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