CM1293A-04SO
4-Channel
Low Capacitance
ESD Protection Array
Product Description
CM1293A−04SO has been designed to provide ESD protection for
electronic components or subsystems requiring minimal capacitive
loading. This device is ideal for protecting systems with high data and
clock rates or for circuits requiring low capacitive loading. Each ESD
channel consists of a pair of diodes in series that steer the positive or
negative ESD current pulse to either the positive (V
P
) or negative (V
N
)
supply rail. A Zener diode is embedded between V
P
and V
N
which
helps protect the V
CC
rail against ESD strikes. This device protects
against ESD pulses up to
8
kV contact discharge) per the
IEC 61000−4−2 Level 4 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (FireWire
, i.LINKt),
Serial ATA, DVI, HDMI, and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
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SC−74
SO SUFFIX
CASE 318F
BLOCK DIAGRAM
VP
CH1
CH2
CH3
CH4
CM1293A−04SO
VN
Four Channels of ESD Protection
Provides ESD Protection to IEC61000−4−2
MARKING DIAGRAM
8
kV Contact Discharge
Low Loading Capacitance of 2.0 pF Max
Low Clamping Voltage
Channel I/O to I/O Capacitance 1.5 pF Typical
Zener Diode Protects Supply Rail and Eliminates the Need for
External By−Pass Capacitors
Each I/O Pin Can Withstand over 1000 ESD Strikes*
This Device is Pb−Free and is RoHS Compliant**
XXXMG
G
1
XXX
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
Applications
DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
Serial ATA Ports in Desktop PCs and Hard Disk Drives
PCI Express Ports
General Purpose High−Speed Data Line ESD Protection
ORDERING INFORMATION
Device
CM1293A−04SO
Package
SC−74
(Pb−Free)
Shipping
†
3,000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
**Standard test condition is IEC61000−4−2 level 4 test circuit with each pin
subjected to
8
kV contact discharge for 1000 pulses. Discharges are timed at
1 second intervals and all 1000 strikes are completed in one continuous test run.
The part is then subjected to standard production test to verify that all of the
tested parameters are within spec after the 1000 strikes.
**For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2012
January, 2012
−
Rev. 0
1
Publication Order Number:
CM1293A−04SO/D
CM1293A−04SO
Table 1. PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
Name
CH1
V
N
CH2
CH3
V
P
CH4
Type
I/O
GND
I/O
I/O
PWR
I/O
Description
ESD Channel
Negative Voltage Supply Rail
ESD Channel
ESD Channel
Positive Voltage Supply Rail
ESD Channel
CH1
635
V
N
CH2
PACKAGE/PINOUT DIAGRAM
Top View
CH4
V
P
CH3
4−Channel SC−74
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Supply Voltage (V
P
−
V
N
)
Operating Temperature Range
Storage Temperature Range
DC Voltage at any Channel Input
Rating
6.0
–40 to +85
–65 to +150
(V
N
−
0.5) to (V
P
+ 0.5)
Units
V
C
C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Package Power Rating
Rating
–40 to +85
225
Units
C
mW
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(Note 1)
Symbol
V
P
I
P
V
F
I
LEAK
C
IN
DC
IO
V
ESD
Parameter
Operating Supply Voltage (V
P
−V
N
)
Operating Supply Current
Diode Forward Voltage
Channel Leakage Current
Channel Input Capacitance
Channel I/O to I/O Capacitance
ESD Protection
Peak Discharge Voltage at any
Channel Input, in System
Contact Discharge per
IEC 61000−4−2 Standard
Channel Clamp Voltage
Positive Transients
Negative Transients
Dynamic Resistance
Positive Transients
Negative Transients
(V
P
−V
N
) = 3.3 V
I
F
= 8 mA, T
A
= 25C
T
A
= 25C, V
P
= 5 V, V
N
= 0 V
At 1 MHz, V
P
= 3.3 V, V
N
= 0 V, V
IN
= 1.65 V
1.5
0.90
0.1
1.0
2.0
Conditions
Min
Typ
3.3
Max
5.5
8.0
Units
V
mA
V
mA
pF
pF
kV
T
A
= 25C (Notes 2 and 3)
T
A
= 25C, I
PP
= 1A, t
P
= 8/20
mS
(Note 3)
T
A
= 25C, I
PP
= 1A, t
P
= 8/20
mS
(Note 3)
8
V
V
CL
+9.9
–1.6
0.96
0.5
R
DYN
W
1. All parameters specified at T
A
= –40C to +85C unless otherwise noted.
2. Standard IEC 61000−4−2 with C
Discharge
= 150 pF, R
Discharge
= 330
W,
V
P
= 3.3 V, V
N
grounded.
3. These measurements performed with no external capacitor on V
P
.
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CM1293A−04SO
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of C
IN
vs. V
IN
(f = 1 MHz, V
P
= 3.3 V, V
N
= 0 V, 0.1
mF
Chip Capacitor between V
P
and V
N
, 255C)
Figure 2. Typical Variation of C
IN
vs. Temp
(f = 1 MHz, V
IN
= 30 mV, V
P
= 3.3 V, V
N
= 0 V, 0.1
mF
Chip Capacitor between V
P
and V
N
)
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3
CM1293A−04SO
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50
W
Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, V
P
= 3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, V
P
= 3.3 V)
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CM1293A−04SO
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a
connector) and the ESD protection device. Refer to Figure 5, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to the power supply is represented by L
1
and L
2
. The voltage V
CL
on the
line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
) / dt+ L
2
x d(I
ESD
) / dt
where I
ESD
is the ESD current pulse, and V
SUPPLY
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
ESD
)/dt can be
approximated by
DI
ESD
/Dt, or 30/(1x10
−9
). So just 10 nH of series inductance (L
1
and L
2
combined) will lead to a 300 V
increment in V
CL
!
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between V
P
and V
N
. This greatly reduces the effect of supply rail inductance
L
2
on V
CL
by clamping V
P
at the breakdown voltage of the Zener diode. However, for the lowest possible V
CL
, especially when
V
P
is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22
F
ceramic chip
capacitor be connected between V
P
and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
L
2
V
P
POSITIVE SUPPLY RAIL
V
CC
PATH OF ESD CURRENT PULSE I
ESO
D
1
L
1
CHANNEL
INPUT
0.22
mF
LINE BEING
PROTECTED
D
2
ONE
CHANNEL
25 A
V
CL
0A
V
N
GROUND RAIL
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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BEING
PROTECTED
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