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NLSX3018DTR2G

产品类别逻辑    逻辑   
文件大小145KB,共12页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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NLSX3018DTR2G规格参数

参数名称属性值
Brand NameON Semiconductor
是否无铅不含铅
厂商名称ON Semiconductor(安森美)
零件包装代码TSSOP
包装说明TSSOP-20
针数20
制造商包装代码9.48
Reach Compliance Codecompliant
Factory Lead Time4 weeks
Samacsys DescriptionTranslation - Voltage Levels 8 BIT TRANSLATOR
系列3018
JESD-30 代码R-PDSO-G20
JESD-609代码e4
长度6.5 mm
逻辑集成电路类型BUS DRIVER
湿度敏感等级1
位数4
功能数量1
端口数量2
端子数量20
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)260
传播延迟(tpd)9.3 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)4.5 V
最小供电电压 (Vsup)1.3 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
温度等级INDUSTRIAL
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度4.4 mm

文档预览

下载PDF文档
NLSX3018
8-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3018 is a 8−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O V
CC
and I/O
V
L
−ports
are designed to track two different power supply rails, V
CC
and V
L
respectively. The V
CC
supply rail is configurable from 1.3 V
to 4.5 V while the V
L
supply rail is configurable from 0.9 V to (V
CC
0.4) V. This allows lower voltage logic signals on the V
L
side to be
translated into higher voltage logic signals on the V
CC
side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both V
CC
and V
L
. The EN signal is designed to track
V
L
.
Features
http://onsemi.com
MARKING
DIAGRAMS
UDFN20
MU SUFFIX
CASE 517AK
LA
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
20
SOIC−20
DW SUFFIX
CASE 751D
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
NLSX3018
AWLYYWWG
LAM
G
Wide High−Side V
CC
Operating Range: 1.3 V to 4.5 V
Wide Low−Side V
L
Operating Range: 0.9 V to (V
CC
0.4) V
High−Speed with 100 Mb/s Guaranteed Date Rate for V
L
> 1.6 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−preferential Powerup Sequencing
Small packaging: 4.0 mm x 2.0 mm UDFN20
This is a Pb−Free Device
Typical Applications
Mobile Phones, PDAs, Other Portable Devices
PIN ASSIGNMENT
I/O V
L
1
I/O V
L
2
I/O V
L
3
I/O V
L
4
V
L
EN
I/O V
L
5
I/O V
L
6
I/O V
L
7
I/O V
L
8
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TSSOP−20
DT SUFFIX
CASE 948E
NLSX
3018
ALYWG
G
I/O V
CC
1
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
V
CC
GND
I/O V
CC
5
I/O V
CC
6
I/O V
CC
7
I/O V
CC
8
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
(Top View)
©
Semiconductor Components Industries, LLC, 2013
July, 2013
Rev. 2
1
Publication Order Number:
NLSX3018/D

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