NLAS4684
Ultra-Low Resistance
Dual SPDT Analog Switch
The NLAS4684 is an advanced CMOS analog switch fabricated in
Sub−micron silicon gate CMOS technology. The device is a dual
Independent Single Pole Double Throw (SPDT) switch featuring
Ultra−Low R
ON
of 0.5
W,
for the Normally Closed (NC) switch, and
0.8
W
for the Normally Opened switch (NO) at 2.7 V.
The part also features guaranteed Break Before Make switching,
assuring the switches never short the driver.
The NLAS4684 is available in a 2.0 x 1.5 mm bumped die array.
The pitch of the solder bumps is 0.5 mm for easy handling.
Features
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MARKING
DIAGRAMS
•
Ultra−Low R
ON
,
t0.5
W
at 2.7 V
•
Threshold Adjusted to Function with 1.8 V Control at
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
CC
= 2.7−3.3 V
Single Supply Operation from 1.8−5.5 V
Tiny 2 x 1.5 mm Bumped Die
Low Crosstalk,
t
83 dB at 100 kHz
Full 0−V
CC
Signal Handling Capability
High Isolation,
−65
dB at 100 kHz
Low Standby Current,
t50
nA
Low Distortion,
t0.14%
THD
R
ON
Flatness of 0.15
W
Pin for Pin Replacement for MAX4684
High Continuous Current Capability
$300
mA Through Each Switch
Large Current Clamping Diodes at Analog Inputs
$300
mA Continuous Current Capability
Pb−Free Packages are Available
Cell Phone
Speaker Switching
Power Switching
Modems
Automotive
A1
Microbump−10
CASE 489AA
A1
4684
AYWWG
G
1
1
DFN10
CASE 485C
NLAS
4684
ALYWG
G
Micro10
CASE 846B
1
4684
AYWG
G
Applications
A
= Assembly Location
L
= Wafer Lot
Y
= Year
WW, W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
IN 1, 2
0
1
NO 1, 2
OFF
ON
NC 1, 2
ON
OFF
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
September, 2008
−
Rev. 20
1
Publication Order Number:
NLAS4684/D
NLAS4684
GND
NC2
IN2
COM2
6
7
8
9
5 NC1
4 IN1
3 COM1
2 NO1
1 V
CC
(Top View)
NO2 10
Figure 1. Pin Connections and Logic Diagram
(DFN10 and Micro10)
GND
NC1
C
1
B
1
A
1
NC2
IN1
COM1
NO1
C
2
C
3
C
4
A
2
A
3
A
4
IN2
COM2
NO2
B
4
V
CC
(Top View)
Figure 2. Pin Connections and Logic Diagram
(Microbump−10)
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2
NLAS4684
MAXIMUM RATINGS
Symbol
V
CC
V
IS
V
IN
I
anl1
I
anl−pk 1
I
clmp
I
clmp 1
Positive DC Supply Voltage
Analog Input Voltage (V
NO
, V
NC
, or V
COM
)
Digital Select Input Voltage
Continuous DC Current from COM to NC/NO
Peak Current from COM to NC/NO, 10 duty cycle (Note 1)
Continuous DC Current into COM/NO/NC
Peak Current into Input Clamp Diodes at COM/NC/NO
Parameter
Value
*0.5
to
)7.0
*0.5 v
V
IS
v
V
CC
)0.5
*0.5 v
V
I
v)7.0
$300
$500
$300
$500
Unit
V
V
V
mA
mA
mA
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Defined as 10% ON, 90% off duty cycle.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
IS
T
A
t
r
, t
f
ESD
DC Supply Voltage
Digital Select Input Voltage
Analog Input Voltage (NC, NO, COM)
Operating Temperature Range
Input Rise or Fall Time, SELECT
Human Body Model
−
All Pins
V
CC
= 3.3 V
$
0.3 V
V
CC
= 5.0 V
$
0.5 V
Parameter
Min
1.8
GND
GND
*55
0
0
Max
5.5
5.5
V
CC
)125
100
20
5
Unit
V
V
V
°C
ns/V
kV
DC CHARACTERISTICS
−
Digital Section
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage, Select Inputs
(Figure 9)
Condition
V
CC
$10%
2.0
2.5
3.0
5.0
2.0
2.5
3.0
5.0
V
IN
= 5.5 V or GND
V
IN
= 5.5 V or GND
Select and V
IS
= V
CC
or GND
5.5
0
5.5
*555C
to 255C
1.4
1.4
1.4
2.0
0.5
0.5
0.5
0.8
$
1.0
$10
$
180
t855C
1.4
1.4
1.4
2.0
0.5
0.5
0.5
0.8
$
1.0
$10
$
200
t1255C
1.4
1.4
1.4
2.0
0.5
0.5
0.5
0.8
$
1.0
$10
$
200
Unit
V
V
IL
Maximum Low−Level Input
Voltage, Select Inputs
(Figure 9)
V
I
IN
I
OFF
I
CC
Maximum Input Leakage
Current, Select Inputs
Power Off Leakage Current
Maximum Quiescent Supply
Current (Note 2)
mA
mA
nA
2. Guaranteed by design.
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3
NLAS4684
DC ELECTRICAL CHARACTERISTICS
−
Analog Section
Guaranteed Maximum Limit
−555C
to 255C
Symbol
R
ON
(NC)
Parameter
NC “ON” Resistance
(Note 3)
NO “ON” Resistance
(Note 3)
NC_On−Resistance
Flatness (Notes 3, 5)
NO_On−Resistance
Flatness (Notes 3, 5)
On−Resistance Match
Between Channels
(Notes 3 and 4)
Condition
V
IN
v
V
IL
V
IS
= GND to V
CC
I
IN
I
v
100 mA
V
IN
w
V
IH
V
IS
= GND to V
CC
I
IN
I
v
100 mA
I
COM
= 100 mA
V
IS
= 0 to V
CC
I
COM
= 100 mA
V
IS
= 0 to V
CC
V
IS
= 1.3 V;
I
COM
= 100 mA
V
IS
= 1.5 V;
I
COM
= 100 mA
V
IS
= 2.8 V;
I
COM
= 100 mA
V
IN
= V
IL
or V
IH
V
NO
or V
NC
= 1.0
V
COM
= 4.5 V
V
IN
= V
IL
or V
IH
V
NO
1.0 V or 4.5 V with
V
NC
floating or
V
NC
1.0 V or 4.5 V with
V
NO
floating
V
COM
= 1.0 V or 4.5 V
V
CC
$10%
2.5
3.0
5.0
2.5
3.0
5.0
2.5
3.0
5.0
2.5
3.0
5.0
2.5
3.0
5.0
5.5
−1
Min
Max
0.6
0.5
0.4
1.0
0.8
0.8
0.15
0.15
0.15
0.35
0.35
0.35
0.18
0.06
0.06
1
−10
t855C
Min
Max
0.7
0.5
0.4
1.0
0.8
0.8
0.15
0.15
0.15
0.35
0.35
0.35
0.18
0.06
0.06
10
−100
t1255C
Min
Max
0.8
0.5
0.5
1.0
1.0
0.9
0.15
0.15
0.15
0.35
0.35
0.35
0.18
0.06
0.06
100
nA
Unit
W
R
ON
(NO)
W
R
FLAT (NC)
W
R
FLAT (NO)
W
DR
ON
W
I
NC(OFF)
I
NO(OFF)
I
COM(ON)
NC or NO Off
Leakage Current
(Figure 13) (Note 3)
COM ON
Leakage Current
(Figure 13) (Note 3)
5.5
−2
2
−20
20
−200
200
nA
3. Guaranteed by design. Resistance measurements do not include test circuit or package resistance.
4.
DR
ON =
R
ON(MAX)
−
R
ON(MIN)
between NC1 and NC2 or between NO1 and NO2.
5. Flatness is defined as the difference between the maximum and minimum value of on−resistance as measured over the specified analog
signal ranges.
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4
NLAS4684
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns) (Typical characteristics are at 25°C)
Guaranteed Maximum Limit
Symbol
t
ON
Parameter
Turn−On Time
Test Conditions
R
L
= 50
W,
C
L
= 35 pF
(Figures 4 and 5)
R
L
= 50
W,
C
L
= 35 pF
(Figures 4 and 5)
V
IS
= 3.0
R
L
= 300
W,
C
L
= 35 pF
(Figure 3)
V
CC
(V)
2.5
3.0
5.0
2.5
3.0
5.0
3.0
V
IS
(V)
1.3
1.5
2.8
1.3
1.5
2.8
1.5
2
15
*555C
to 255C
Min
Typ
Max
60
50
30
50
40
30
t855C
Min
Max
70
60
35
55
50
35
t1255C
Min
Max
70
60
35
55
50
35
Unit
ns
t
OFF
Turn−Off Time
ns
t
BBM
Minimum Break−Before−Make
Time (Note 6)
ns
Typical @ 25, V
CC
= 5.0 V
C
NC
Off
C
NO
Off
C
NC
On
C
NO
On
NC Off Capacitance, f = 1 MHz
NO Off Capacitance, f = 1 MHz
NC On Capacitance, f = 1 MHz
NO On Capacitance, f = 1 MHz
102
104
322
330
pF
ADDITIONAL APPLICATION CHARACTERISTICS
(Voltages Referenced to GND Unless Noted)
Symbol
BW
Parameter
Maximum On−Channel
−3dB
Bandwidth or Minimum Frequency
Response
Maximum Feed−through On Loss
Off−Channel Isolation (Note 7)
Charge Injection Select Input to
Common I/O (Figures 10 and 11)
Total Harmonic Distortion THD +
Noise (Figure 9)
Channel−to−Channel Crosstalk
Condition
V
IN
=
0 dBm
V
IN
centered between V
CC
and GND
(Figure 6)
V
IN
=
0 dBm @ 100 kHz to 50 MHz
V
IN
centered between V
CC
and GND (Figure 6)
f = 100 kHz; V
IS
=
1 V RMS; C
L
= 5 nF
V
IN
centered between V
CC
and GND(Figure 6)
V
IN =
V
CC to
GND, R
IS
= 0
W,
C
L
= 1 nF
Q = C
L
−
DV
OUT
(Figure 7)
F
IS
= 20 Hz to 100 kHz, R
L
= R
gen
= 600
W,
C
L
= 50 pF
V
IS
=
1 V RMS
f = 100 kHz; V
IS
=
1 V RMS,
C
L
= 5 pF, R
L
= 50
W
V
IN
centered between V
CC
and GND (Figure 6)
NC
NO
V
CC
V
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Typical
255C
6.5
9.5
−0.05
−65
15
0.14
−83
pC
%
dB
dB
dB
Unit
MHz
V
ONL
V
ISO
Q
THD
VCT
6.
−55°C
specifications are guaranteed by design.
7. Off−Channel Isolation = 20log10 (Vcom/Vno) (See Figure 6).
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5
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