Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. h
FE(1)
/h
FE(2)
is the ratio of one transistor compared to the other transistor within the same package. The smaller h
FE
is used as numerator.
3. V
BE(1)
− V
BE(2)
is the absolute difference of one transistor compared to the other transistor within the same package.
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2
NST65011MW6
TYPICAL CHARACTERISTICS
2.0
hFE , NORMALIZED DC CURRENT GAIN
1.5
1.0
0.8
0.6
0.4
0.3
0.2
V
CE
= 10 V
T
A
= 25°C
V, VOLTAGE (VOLTS)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.2
0.5
50
1.0
20
2.0
5.0 10
I
C
, COLLECTOR CURRENT (mAdc)
100
200
0
0.1
V
CE(sat)
@ I
C
/I
B
= 10
0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30
I
C
, COLLECTOR CURRENT (mAdc)
50 70 100
V
BE(on)
@ V
CE
= 10 V
T
A
= 25°C
V
BE(sat)
@ I
C
/I
B
= 10
Figure 1. Normalized DC Current Gain
2.0
VCE , COLLECTOR-EMITTER VOLTAGE (V)
T
A
= 25°C
1.6
I
C
= 200 mA
1.2
I
C
=
I
C
=
10 mA 20 mA
0.8
I
C
= 50 mA
I
C
= 100 mA
θ
VB, TEMPERATURE COEFFICIENT (mV/
°
C)
1.0
Figure 2. “Saturation” and “On” Voltages
-55°C to +125°C
1.2
1.6
2.0
2.4
2.8
0.4
0
0.02
0.1
1.0
I
B
, BASE CURRENT (mA)
10
20
0.2
10
1.0
I
C
, COLLECTOR CURRENT (mA)
100
Figure 3. Collector Saturation Region
10
7.0
C, CAPACITANCE (pF)
5.0
C
ib
T
A
= 25°C
f T, CURRENT-GAIN - BANDWIDTH PRODUCT (MHz)
400
300
200
Figure 4. Base−Emitter Temperature Coefficient
3.0
C
ob
2.0
100
80
60
40
30
20
0.5 0.7
V
CE
= 10 V
T
A
= 25°C
1.0
0.4 0.6 0.8 1.0
2.0
4.0 6.0 8.0 10
V
R
, REVERSE VOLTAGE (VOLTS)
20
40
1.0
2.0 3.0
5.0 7.0 10
20
I
C
, COLLECTOR CURRENT (mAdc)
30
50
Figure 5. Capacitances
Figure 6. Current−Gain − Bandwidth Product
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3
NST65011MW6
TYPICAL CHARACTERISTICS
200
1s
IC, COLLECTOR CURRENT (mA)
100
50
T
A
= 25°C
T
J
= 25°C
3 ms
The safe operating area curves indicate I
C
−V
CE
limits
of the transistor that must be observed for reliable
operation. Collector load lines for specific circuits must
fall below the limits indicated by the applicable curve.
The data of Figure 7 is based upon T
J(pk)
= 150°C; T
C
or T
A
is variable depending upon conditions.
10
5.0
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
5.0
10
30 45
V
CE
, COLLECTOR-EMITTER VOLTAGE (V)
65
100
2.0
1.0
Figure 7. Active Region Safe Operating Area
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4
NST65011MW6
PACKAGE DIMENSIONS
SC−88 (SOT−363)
CASE 419B−02
ISSUE Y
aaa H D
D
A
D
5
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
2X
H
GAGE
PLANE
6
L2
E
1
2X
2
3
L
DETAIL A
E1
aaa C
bbb H D
2X 3 TIPS
e
B
TOP VIEW
6X
b
ddd
M
C A-B D
A2
A
DETAIL A
6X
ccc C
SIDE VIEW
A1
C
SEATING
PLANE
c
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
6X
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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