74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
March 1995
Revised February 2005
74LCX14
Low Voltage Hex Inverter
with 5V Tolerant Schmitt Trigger Inputs
General Description
The LCX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LCX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs
s
2.3V–3.6V V
CC
specifications provided
s
6.5 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
3.0V)
s
Power down high impedance inputs and outputs
s
r
24 mA output drive (V
CC
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds JEDEC 78 conditions
s
ESD performance:
Machine model
!
200V
Human model
!
2000V
s
Leadless Pb-Free DQFN package
Ordering Code:
Order Number
74LCX14M
74LCX14MX_NL
(Note 2)
74LCX14SJ
74LCX14BQX
(Note 1)
74LCX14MTC
74LCX14MTCX_NL
(Note 2)
Package
Number
M14A
M14A
M14D
MLP014A
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
DQFN package available in Tape and Reel only.
Note 2:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS012412
www.fairchildsemi.com
74LCX14
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in HIGH or LOW State (Note 4)
V
I
GND
V
O
GND
V
O
!
V
CC
V
mA
mA
mA
mA
mA
0.5 to
7.0
0.5 to
7.0
0.5 to V
CC
0.5
50
50
50
r
50
r
100
r
100
65 to
150
q
C
Recommended Operating Conditions
(Note 5)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
V
CC
V
CC
V
CC
3.0V
3.6V
2.7V
3.0V
2.3V
2.7V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
Max
3.6
3.6
5.5
V
CC
Units
V
V
V
mA
r
24
r
12
r
8
Note 3:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4:
I
O
Absolute Maximum Rating must be observed.
Note 5:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
t
V
t
V
H
V
OH
Parameter
Positive Input Threshold
Negative Input Threshold
Hysteresis
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
I
I
OFF
I
CC
Input Leakage Current
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
Conditions
V
CC
(V)
2.5
3.0
2.5
3.0
2.5
3.0
T
A
40
q
C to
85
q
C
Max
1.7
2.2
1.1
1.5
1.0
1.2
Min
0.9
1.2
0.4
0.6
0.3
0.4
V
CC
- 0.2
1.8
2.2
2.4
2.2
Units
V
V
V
100
P
A
12 mA
18 mA
24 mA
100
P
A
12 mA
16 mA
24 mA
5.5V
2.3
3.6
2.3
2.7
3.0
3.0
2.3
3.6
2.3
2.7
3.0
3.0
2.3
3.6
0
2.3
3.6
2.3
3.6
2.3
3.6
I
OH
= -8 mA
V
0.2
0.6
0.4
0.4
0.55
V
I
OL
= 8mA
0
d
V
I
d
5.5V
V
I
or V
O
V
I
V
IH
V
CC
or GND
V
CC
0.6V
r
5.0
10
10
P
A
P
A
P
A
P
A
3.6V
d
V
I
d
5.5V
r
10
500
'
I
CC
3
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74LCX14
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
3.3V
r
0.3V
40
q
C to
85
q
C, R
L
V
CC
C
L
Min
1.5
1.5
2.7V
50 pF
Max
7.5
7.5
500
:
V
CC
C
L
Min
1.5
1.5
2.5V
r
0.2V
30 pF
Max
7.8
7.8
ns
ns
Units
C
L
50 pF
Min
t
PHL
t
PLH
t
OSHL
t
OSLH
Output to Output Skew
(Note 6)
Propagation Delay Time
1.5
1.5
Max
6.5
6.5
1.0
1.0
Note 6:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
C
L
C
L
C
L
C
L
Conditions
50 pF, V
IH
3.3V, V
IL
30 pF, V
IH
50 pF, V
IH
2.5V, V
IL
3.3V, V
IL
0V
0V
0V
0V
V
CC
(V)
3.3
2.5
3.3
2.5
T
A
25
q
C
0.8
0.6
Typical
Units
V
V
0.8
0.6
30 pF, V
IH
2.5V, V
IL
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
CC
V
CC
V
CC
Open, V
I
3.3V, V
I
3.3V, V
I
Conditions
0V or V
CC
0V or V
CC
0V or V
CC
, f
10 MHz
Typical
7
8
25
Units
pF
pF
pF
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4
74LCX14
AC Loading and Waveforms
Generic for LCX Family
FIGURE 1. AC Test Circuit
(C
L
includes probe and jig capacitance)
Test
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
,t
PHZ
Switch
Open
6V at V
CC
3.3
r
0.3V
V
CC
x 2 at V
CC
2.5
r
0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and t
rec
Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable TImes for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f = 1MHz, t
r
= t
f
= 3ns)
V
CC
Symbol
V
mi
V
mo
V
x
V
y
3.3V
r
0.3V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
2.7V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
2.5V
r
0.2V
V
CC
/2
V
CC
/2
V
OL
0.15V
V
OH
0.15V
5
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