74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
February 2006
74LCX373
Low Voltage Octal Transparent Latch
with 5V Tolerant Inputs and Outputs
Features
■
5V tolerant inputs and outputs
■
2.3V–3.6V V
CC
specifications provided
■
8.0ns t
PD
max (V
CC
= 3.3V), 10
µ
A I
CC
max
■
Power down high impedance inputs and outputs
■
Supports live insertion/withdrawal
1
■
±
24mA output drive (V
CC
= 3.0V)
■
Implements patented noise/EMI reduction circuitry
■
Latch-up performance exceeds JEDEC 78 conditions
■
ESD performance
General Description
The LCX373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The device is
designed for low voltage applications with capability of
interfacing to a 5V signal environment.
The LCX373 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
– Human body model
>
2000V
– Machine model
>
200V
■
Leadless Pb-Free DQFN package
Ordering Information
Order
Number
74LCX373WM
74LCX373SJ
74LCX373BQX
2
74LCX373MSA
74LCX373MTC
74LCX373MTCX_NL
3
Package
Number
M20B
M20D
MLP020B
MSA20
MTC20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads
(DQFN), JEDEC MO-241, 2.5 x 4.5mm
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm
Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Notes:
1. To ensure the high impedance state during power up or down, OE should be tied to V
CC
through a pull-up resistor: the minimum
value of the resistor is determined by the current-sourcing capability of the driver.
2. DQFN package available in Tape and Reel only.
3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
©2006 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
74LCX373 Rev. 2.0.0
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Logic Symbols
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
IEEE/IEC
OE
LE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
EN
C1
1D
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
Truth Table
Inputs
LE
X
H
H
L
Outputs
D
n
X
L
H
X
OE
H
L
L
L
O
n
Z
L
H
O
0
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition of Latch
Enable
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
Functional Description
The LCX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e. a latch output
will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2-state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Pad Assignments for DQFN
OE V
CC
1
20
19
18
17
16
15
14
13
12
10
11
O
0
2
D
0
3
D
1
4
O
1
5
O
2
6
D
2
7
D
3
8
O
3
9
GND LE
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
(Top View)
2
74LCX373 Rev. 2.0.0
www.fairchildsemi.com
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Logic Diagram
D
0
D
O
D
1
D
O
D
2
D
O
D
3
D
O
D
4
D
O
D
5
D
O
D
6
D
O
D
7
D
O
G
LE
G
G
G
G
G
G
G
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
3
74LCX373 Rev. 2.0.0
www.fairchildsemi.com
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Absolute Maximum Ratings
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the
conditions for actual device operation.
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Conditions
Value
−
0.5 to
+
7.0
−
0.5 to
+
7.0
Units
V
V
V
mA
mA
mA
mA
mA
°
C
Output in 3-STATE
Output in HIGH or LOW State
4
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
−
0.5 to
+
7.0
−
0.5 to V
CC
+
0.5
−
50
−
50
+
50
±
50
±
100
±
100
−
65 to
+
150
Recommended Operating Conditions
5
Symbol
V
CC
V
I
V
O
I
OH
/ I
OL
Parameter
Supply Voltage
Input Voltage
Output Voltage
Output Current
Conditions
Operating
Data Retention
HIGH or LOW State
3-STATE
V
CC
= 3.0V
−
3.6V
V
CC
= 2.7V
−
3.0V
V
CC
= 2.3V
−
2.7V
Min.
2.0
1.5
0
0
0
Max.
3.6
3.6
5.5
V
CC
5.5
±
24
±
12
±
8
Units
V
V
V
mA
T
A
∆
t /
∆
V
Free-Air Operating Temperature
Input Edge Rate
V
IN
= 0.8V
−
2.0V, V
CC
= 3.0V
−
40
0
85
10
°
C
ns /V
Notes:
4. I
O
Absolute Maximum Rating must be observed.
5. Unused inputs must be held HIGH or LOW. They may not float.
4
74LCX373 Rev. 2.0.0
www.fairchildsemi.com
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
DC Electrical Characteristics
T
A
=
−
40
°C
to
+85°C
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
Conditions
V
CC
(V)
2.3
−
2.7
2.7
−
3.6
2.3
−
2.7
2.7
−
3.6
Min.
1.7
2.0
Max.
Units
V
0.7
0.8
V
CC
−
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
±5.0
10
10
±10
500
V
V
I
OH
=
−100 µA
I
OH
=
−8
mA
I
OH
=
−12
mA
I
OH
=
−18
mA
I
OH
=
−24
mA
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
−
3.6
0
2.3
−
3.6
2.3
−
3.6
2.3
−
3.6
V
OL
LOW Level Output Voltage
I
OL
= 100
µA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 16 mA
I
OL
= 24 mA
V
I
I
I
OZ
I
OFF
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
5.5V
0
≤
V
O
≤
5.5V,
V
I
= V
IH
or V
IL
V
I
or V
O
= 5.5V
V
I
= V
CC
or GND
3.6V
≤
V
I
, V
O
≤
5.5V
6
V
IH
= V
CC
−0.6V
µA
µA
µA
µA
µA
AC Electrical Characteristics
T
A
=
−40°C
to
+85°C,
R
L
= 500
Ω
V
CC
= 3.3V
±
0.3V
C
L
= 50pF
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
S
t
H
t
W
V
CC
= 2.7V
C
L
= 50pF
Min.
1.5
1.5
1.5
1.5
2.5
1.5
3.3
V
CC
= 2.5
±
0.2V
C
L
= 30pF
Min.
1.5
1.5
1.5
1.5
4.0
2.0
4.0
Parameter
Propagation Delay, D
n
to O
n
Propagation Delay, LE to O
n
Output Enable Time
Output Disable Time
Setup Time, D
n
to LE
Hold Time, D
n
to LE
LE Pulse Width
Min.
1.5
1.5
1.5
1.5
2.5
1.5
3.3
Max.
8.0
8.5
8.5
7.5
Max.
9.0
9.5
9.5
8.5
Max.
9.6
10.5
10.5
9.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
t
OSHL,
t
OSLH
Output to Output Skew
7
1.0
Notes:
6. Outputs disabled or 3-STATE only.
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs
of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or
LOW-to-HIGH (t
OSLH
).
5
74LCX373 Rev. 2.0.0
www.fairchildsemi.com
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