NDT451AN
N-Channel Enhancement Mode Field Effect Transistor
General Description
Power SOT N-Channel enhancement mode power field
effect
transistors
are
produced
using
ON
Semiconductor's
proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance and provide
superior switching performance. These devices are
particularly suited for low voltage applications such as DC
motor control and DC/DC conversion where fast switching,
low in-line power loss, and resistance to transients are
needed.
Features
7.2A, 30V. R
DS(ON)
= 0.035
Ω
@ V
GS
= 10V
R
DS(ON)
= 0.05
Ω
@ V
GS
= 4.5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
________________________________________________________________________________
D
G
D
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
T
A
= 25°C unless otherwise noted
NDT451AN
30
± 20
(Note 1a)
Units
V
V
A
W
± 7.2
± 25
3
1.3
1.1
-65 to 150
42
12
(Note 1a)
(Note 1b)
(Note 1c)
T
J
,T
STG
Operating and Storage Temperature Range
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
°C
°C/W
°C/W
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
(Note 1a)
(Note 1)
@ 2009
Semiconductor Components Industries, LLC.
September-2017,
Rev.
4
Publication Order Number:
NDT451AN/D
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Parameter
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
Gate Threshold Voltage
Static Drain-Source On-Resistance
Conditions
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55°C
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125°C
V
GS
= 10 V, I
D
= 7.2 A
T
J
= 125°C
V
GS
= 4.5 V, I
D
= 6.0 A
T
J
= 125°C
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 10 V,
I
D
= 7.2 A, V
GS
= 10 V
V
DD
= 10 V, I
D
= 1 A,
V
GEN
= 10 V, R
GEN
= 6
Ω
V
GS
= 10 V, V
DS
= 5 V
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 7.2 A
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
720
370
250
12
13
29
10
19
2.3
5.5
20
30
50
20
30
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
25
15
11
S
1
0.7
1.6
1.2
0.03
0.042
0.042
0.058
Min
30
1
10
100
-100
3
2.2
0.035
0.063
0.05
0.09
A
Typ
Max
Units
V
µA
µA
nA
nA
V
OFF CHARACTERISTICS
ON CHARACTERISTICS
(Note 2)
Ω
SWITCHING CHARACTERISTICS
(Note 2)
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2
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
I
S
V
SD
t
rr
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max
2.3
Units
A
V
ns
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
S
= 7.2A
(Note 2)
0.9
1.3
100
V
GS
= 0 V, I
F
= 1.25 A, dI
F
/dt = 100 A/µs
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
T
J
−
T
A
R
θ
J C
R
θ
CA
t
)
+
(
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 95
o
C/W when mounted on a 0.066 in
2
pad of 2oz copper.
c. 110
o
C/W when mounted on a 0.0123 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
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Typical Electrical Characteristics
25
V
GS
=10V
3
6.0 5.0
DRAIN-SOURCE ON-RESISTANCE
4.5
4.0
R
DS(ON)
, NORMALIZED
V
GS
= 3.0V
2.5
I
D
, DRAIN-SOURCE CURRENT (A)
20
3.5
4.0
4.5
5.0
6.0
10
15
2
3.5
10
1.5
5
3.0
1
0
0
0.5
1
1.5
2
V
DS
, DRAIN-SOURCE VOLTAGE (V)
2.5
3
0.5
0
5
10
15
I
D
, DRAIN CURRENT (A)
20
25
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
2
DRAIN-SOURCE ON-RESISTANCE
1.4
R
DS(ON)
, NORMALIZED
V
GS
=10V
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 7.2A
V
GS
= 10V
1.75
1.5
1.25
1.2
TJ = 125°C
1
25°C
1
0.75
0.5
0.8
-55°C
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0
5
10
15
I
D
, DRAIN CURRENT (A)
20
25
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
25
1.2
20
I
D
, DRAIN CURRENT (A)
125°C
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= 10V
TJ = -55°C
25°C
1.1
1
0.9
0.8
0.7
0.6
-50
V
DS
= V
GS
I
D
= 250µA
15
10
5
0
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
6
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
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Typical Electrical Characteristics
1.1
DRAIN-SOURCE BREAKDOWN VOLTAGE
25
I
1.05
D
= 250µA
I
S
, REVERSE DRAIN CURRENT (A)
10
V
GS
=0V
BV
DSS
, NORMALIZED
1
TJ = 125°C
0.1
1
25°C
-55°C
0.95
0.01
0.9
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0.2
0.4
0.6
0.8
1
1.2
1.4
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
.
2000
1500
1000
CAPACITANCE (pF)
V
GS
, GATE-SOURCE VOLTAGE (V)
10
I
D
= 7.2A
8
V
DS
= 5V
10V
20V
C iss
500
C oss
6
4
200
f = 1 MHz
V
GS
= 0V
C rss
2
100
0.1
0.2
V
0.5
DS
1
2
5
10
20
30
0
0
5
, DRAIN TO SOURCE VOLTAGE (V)
10
15
Q
g
, GATE CHARGE (nC)
20
25
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
20
g
FS
, TRANSCONDUCTANCE (SIEMENS)
V
DS
= 10V
16
TJ = -55°C
25°C
12
8
125°C
4
0
0
5
10
15
20
25
I
D
, DRAIN CURRENT (A)
Figure 11. Transconductance Variation with Drain
Current and Temperature.
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