GTL2014
4-bit LVTTL to GTL transceiver
Rev. 3 — 14 June 2012
Product data sheet
1. General description
The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface
with a GTL−/GTL/GTL+ bus, where GTL−/GTL/GTL+ refers to the reference voltage of the
GTL bus and the input/output voltage thresholds associated with it.
The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or
as a LVTTL to GTL interface.
The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.
The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used
in higher voltage open-drain output applications.
GTL2014 is pin-to-pin backward compatible to the GTL2005 (labels for A port and B port
are interchanged). GTL2014’s V
ref
tracks down to 0.5 V for low voltage CPU, propagation
delays are slightly longer, while GTL2005’s V
ref
linearity degrades below 0.8 V and has
shorter propagation delay.
fast t
PD
GTL2005
GTL2014
slow t
PD
GTL−
GTL
GTL+
002aab378
Fig 1.
GTL2005/GTL2014 positioning
2. Features and benefits
Operates as a 4-bit GTL−/GTL/GTL+ sampling receiver or as a LVTTL to
GTL−/GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V
ref
adjustable from 0.5 V to V
CC
/2
Partial power-down permitted
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-CC101
NXP Semiconductors
GTL2014
4-bit LVTTL to GTL transceiver
Latch-up protection exceeds 500 mA per JESD78
Package offered: TSSOP14
3. Quick reference data
Table 1.
Quick reference data
T
amb
= 25
°
C
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
C
i
C
io
Parameter
LOW to HIGH propagation delay
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW propagation delay
input capacitance
input/output capacitance
Conditions
An-to-Bn; C
L
= 50 pF; V
CC
= 3.3 V
An-to-Bn; C
L
= 50 pF; V
CC
= 3.3 V
Bn-to-An; C
L
= 50 pF; V
CC
= 3.3 V
Bn-to-An; C
L
= 50 pF; V
CC
= 3.3 V
control inputs; V
I
= 3.0 V or 0 V
A port; V
O
= 3.0 V or 0 V
B port; V
O
= V
TT
or 0 V
Min
-
-
-
-
-
-
-
Typ
2.8
3.4
5.2
4.9
2
4.6
3.4
Max
-
-
-
-
2.5
6
4.3
Unit
ns
ns
ns
ns
pF
pF
pF
4. Ordering information
Table 2.
Ordering information
Package
Name
GTL2014PW
TSSOP14
Description
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
Version
SOT402-1
Type number
Standard packing quantities and other packaging data are available at
www.nxp.com/packages/.
4.1 Ordering options
Table 3.
Ordering options
Topside mark
GTL2014
Temperature range
T
amb
=
−40 °C
to +85
°C
Type number
GTL2014PW
GTL2014
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 14 June 2012
2 of 19
NXP Semiconductors
GTL2014
4-bit LVTTL to GTL transceiver
5. Functional diagram
GTL2014
B0
A0
B1
A1
B2
A2
B3
A3
002aab139
VREF
DIR
Fig 2.
Logic diagram for GTL2014
GTL2014
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 14 June 2012
3 of 19
NXP Semiconductors
GTL2014
4-bit LVTTL to GTL transceiver
6. Pinning information
6.1 Pinning
DIR
B0
B1
VREF
B2
B3
GND
1
2
3
4
5
6
7
002aab138
14 V
CC
13 A0
12 A1
GTL2014PW
11 GND
10 A2
9
8
A3
GND
Fig 3.
Pin configuration for TSSOP14
6.2 Pin description
Table 4.
Symbol
DIR
B0
B1
B2
B3
A0
A1
A2
A3
VREF
GND
V
CC
Pin description
Pin
1
2
3
5
6
13
12
10
9
4
7, 8, 11
14
GTL reference voltage
ground (0 V)
positive supply voltage
data inputs/outputs (LVTTL)
Description
direction control input (LVTTL)
data inputs/outputs (GTL)
GTL2014
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 14 June 2012
4 of 19
NXP Semiconductors
GTL2014
4-bit LVTTL to GTL transceiver
7. Functional description
Refer to
Figure 2 “Logic diagram for GTL2014”.
7.1 Function table
Table 5.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
DIR
H
L
Input/output
A (LVTTL)
input
An = Bn
B (GTL)
Bn = An
input
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
I
< 0 V
A port
B port
A port; V
O
< 0 V
output in OFF or HIGH state
A port
B port
I
OL
LOW-level output current
current into any output in the LOW state
A port
B port
I
OH
T
stg
[1]
Conditions
Min
−0.5
-
−0.5
[2]
−0.5
[2]
-
−0.5
[2]
−0.5
[2]
-
-
-
[3]
Max
+4.6
−50
+7.0
+4.6
−50
+7.0
+4.6
32
80
−32
+150
Unit
V
mA
V
V
mA
V
V
mA
mA
mA
°C
HIGH-level output current
storage temperature
current into any output in the HIGH state;
A port
−60
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under
Section 9 “Recommended operating conditions”
is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
[2]
[3]
GTL2014
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 14 June 2012
5 of 19
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