INTEGRATED CIRCUITS
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger
(3-State)
Product specification
1998 Jul 29
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
74LVC574A
FEATURES
•
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•
Supply voltage range of 2.7V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
High impedance when V
CC
= 0V
•
8-bit positive edge-triggered register
•
Independent register and 3-State buffer operation
•
Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC574A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The ’574A’ is functionally identical to the ’374A’, but the ’374A’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
amb
=25°C; t
r
= t
f
v
2.5ns
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
Propagation delay
CP to Q
n
maximum clock frequency
Input capacitance
Power dissipation capacitance per
flip-flop
Notes 1 and 2
CONDITIONS
C
L
= 50pF
V
CC
= 3.3V
TYPICAL
4.8
150
5.0
20
UNIT
ns
MHz
pF
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
mW):
P
D
= C
PD
x V
CC2
x f
i
+
S
(C
L
x V
CC2
x f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
x V
CC2
x f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO)
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE
NORTH AMERICA
74LVC574A D
74LVC574A DB
74LVC574A PW
NORTH AMERICA
74LVC574A D
74LVC574A DB
7LVC574APW DH
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
1998 Jul 29
2
853-1863 19804
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
74LVC574A
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10
11
20
SYMBOL
OE
D0-D7
Q0-Q7
GND
CP
V
CC
FUNCTION
Output enable input (active-Low)
Data inputs
Data outputs
Ground (0V)
Clock input (LOW-to-HIGH,
edge-triggered)
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
1
11
EN
C1
2
3
4
5
6
1D
19
18
17
16
15
14
13
12
PIN CONFIGURATION
7
8
9
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
7
D5
D6
D7
CP
OE
2
3
4
5
6
D0
D1
D2
D3
D4
FF!
to
FF8
SA00402
FUNCTIONAL DIAGRAM
Q0
Q1
Q2
Q3
3-State
OUTPUTS
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
GND 10
SA00400
8
9
11
LOGIC SYMBOL
11
1
SA00403
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
19
18
17
16
15
14
13
12
OE
Q7
1
SA00401
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
74LVC574A
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
FF1
Q
D
CP
FF2
Q
D
CP
FF3
Q
D
CP
Q
D
CP
FF5
Q
D
CP
FF6
Q
D
CP
FF7
Q
D
CP
FF8
Q
FF4
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00404
FUNCTION TABLE
INPUTS
OPERATING MODES
Load and read register
Load register and
disable outputs
H
h
L
l
Z
°
OE
L
L
H
H
LE
°
°
°
°
D
n
l
h
l
h
INTERNAL FLIP-FLOPS
L
H
L
H
OUTPUTS
Q
0
to Q
7
L
H
Z
Z
= HIGH voltage level
= HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition
= LOW voltage level
= LOW voltage level one setup time prior to the LOW-to-HIGH CP transition
= High impedance OFF-state
= LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
DC supply voltage (for max. speed performance)
V
CC
V
I
V
O
T
amb
t
r
, t
f
DC supply voltage (for low-voltage applications)
DC Input voltage range
DC output voltage range; output HIGH or LOW
state
DC output voltage range; output 3-State
Operating ambient temperature range in free-air
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
MIN
2.7
1.2
0
0
0
–40
0
0
MAX
3.6
V
3.6
5.5
V
CC
5.5
+85
20
10
°C
ns/V
V
V
UNIT
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
74LVC574A
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage; output HIGH or LOW state
DC output voltage; output 3-State
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t0
Note 2
V
O
uV
CC
or V
O
t
0
Note 2
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +6.5
"50
–0.5 to V
CC
+0.5
–0.5 to 6.5
"50
"100
–65 to +150
500
500
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
O
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –18mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
OZ
I
off
I
CC
∆I
CC
Input leakage current
2
3-State output OFF-state current
Power off leakage supply
Quiescent supply current
Additional quiescent supply current
per input pin
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= 5.5V or GND
V
CC
= 0.0V; V
I
or V
O
= 5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
"0
1
"0.1
0.1
0.1
0.1
5
GND
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*0.8
0.40
0.20
0.55
"5
"10
"10
10
500
µA
µA
µA
µA
µA
V
V
CC
V
V
CC
2.0
GND
V
0.8
TYP
1
MAX
V
UNIT
V
IL
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1998 Jul 29
5
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