74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 04 — 9 May 2006
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn).
With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3.
With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3.
V
CC
and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
−
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
2. Features
s
Low ON resistance:
x
80
Ω
(typical) at V
CC
−
V
EE
= 4.5 V
x
70
Ω
(typical) at V
CC
−
V
EE
= 6.0 V
x
60
Ω
(typical) at V
CC
−
V
EE
= 9.0 V
s
Logic level translation:
x
To enable 5 V logic to communicate with
±5
V analog signals
s
Typical ‘break before make’ built in
s
Complies with JEDEC standard no. 7A
s
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
3. Applications
s
Analog multiplexing and demultiplexing
s
Digital multiplexing and demultiplexing
s
Signal gating
4. Quick reference data
Table 1:
Quick reference data
V
EE
= GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol Parameter
74HC4053
t
PZH
,
t
PZL
turn-ON time
E to V
os
Sn to V
os
t
PHZ
,
t
PLZ
turn-OFF time
E to V
os
Sn to V
os
C
i
C
S
input capacitance
switch capacitance
independent I/O (nYn)
common I/O (nZ)
C
PD
power dissipation
capacitance
turn-ON time
E to V
os
Sn to V
os
t
PHZ
,
t
PLZ
turn-OFF time
E to V
os
Sn to V
os
C
i
C
S
input capacitance
switch capacitance
independent I/O (nYn)
common I/O(nZ)
C
PD
[1]
Conditions
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
Min
Typ
Max
Unit
-
-
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
-
-
-
-
-
per switch; V
I
= GND to
V
CC
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
-
-
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
-
-
-
-
-
per switch; V
I
= GND to
(V
CC
−
1.5 V)
[1]
[1]
17
21
-
-
ns
ns
18
17
3.5
5
8
36
-
-
-
-
-
-
ns
ns
pF
pF
pF
pF
-
74HCT4053
t
PZH
,
t
PZL
23
21
-
-
ns
ns
20
19
3.5
5
8
36
-
-
-
-
-
-
ns
ns
pF
pF
pF
pF
power dissipation
capacitance
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑{(C
L
+ C
S
)
×
V
CC2
×
f
o
} where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑{(C
L
+ C
S
)
×
V
CC2
×
f
o
} = sum of outputs;
74HC_HCT4053_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 May 2006
2 of 33
Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
C
L
= output load capacitance in pF;
C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in V.
5. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74HC4053
74HC4053N
74HC4053D
74HC4053DB
74HC4053PW
74HC4053BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP16
SO16
SSOP16
TSSOP16
plastic dual in-line package; 16 leads (300 mil); long
body
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Description
Version
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
DIP16
SO16
SSOP16
TSSOP16
plastic dual in-line package; 16 leads (300 mil); long
body
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74HCT4053
74HCT4053N
74HCT4053D
−40 °C
to +125
°C
−40 °C
to +125
°C
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
74HCT4053DB
−40 °C
to +125
°C
74HCT4053PW
−40 °C
to +125
°C
74HCT4053BQ
−40 °C
to +125
°C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
74HC_HCT4053_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 May 2006
3 of 33
Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
6. Functional diagram
E
6
V
CC
16
13 1Y1
S1 11
LOGIC
LEVEL
CONVERSION
DECODER
12 1Y0
14 1Z
1 2Y1
S2 10
2 2Y0
15 2Z
3 3Y1
S3 9
5 3Y0
4 3Z
8
GND
7
V
EE
001aae124
Fig 1. Functional diagram
6
11
10
9
S1
S2
S3
1Y0
1Y1
1Z
2Y0
2Y1
2Z
3Y0
3Y1
6
E
3Z
12
13
14
2
1
15
5
3
4
10
15
#
11
14
#
EN
MUX/DMUX
0
×
0
1
0/1
1
12
13
2
1
9
4
#
5
3
001aae126
001aae125
Fig 2. Logic symbol
74HC_HCT4053_4
Fig 3. IEC logic symbol
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 May 2006
4 of 33
Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Y
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
Z
V
EE
001aad544
Fig 4. Schematic diagram (one switch)
7. Pinning information
7.1 Pinning
74HC4053
74HCT4053
terminal 1
index area
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
GND
(1)
11 S1
10 S2
8
GND
S3
9
2Y1
2
3
4
5
6
7
1
2Y0
16 V
CC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9
001aae127
74HC4053
74HCT4053
2Y1
2Y0
3Y1
3Z
3Y0
E
V
EE
GND
1
2
3
4
5
6
7
8
3Y1
3Z
3Y0
E
V
EE
S3
001aae128
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input.
Fig 5. Pin configuration DIP16, SO16 and
(T)SSOP16
Fig 6. Pin configuration DHVQFN16
74HC_HCT4053_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 9 May 2006
5 of 33
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